Double electron layer tunnelling transistor (DELTT)

We demonstrate the double electron layer tunnelling transistor (DELTT), based on the gate control of two-dimensional-two-dimensional tunnelling in a double quantum well. Unlike previously proposed resonant tunnelling transistors, the DELTT is entirely planar and can be easily fabricated in large numbers. At 1.5 K we demonstrate peak-to-background ratios of :1 in source-drain conductance versus gate voltage and peak-to-valley ratios of :1 in the source-drain current versus source-drain voltage. Using a single DELTT in series with a load resistor, we demonstrate low-power bistable memories at 1.5 K. We also demonstrate a unipolar complementary static RAM by connecting two DELTTs in series.