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A Plan-Generation-Evaluation Framework for Design Space Exploration of Digital Systems Design Jun Kyoung KIM Tag Gon KIM Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E89-A No.3 pp.772-781 Publication Date: 2006/03/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e89-a.3.772 Print ISSN: 0916-8508 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: design space exploration, plan-generation-evaluation framework, graph pruning, attributed AND-OR graph, Full Text: PDF(1.9MB)>>
Summary: Modern digital systems design requires us to explore a large and complex design space to find a best configuration which satisfies design requirements. Such exploration requires a sound representation of design space from which design candidates are efficiently generated, each of which then is evaluated. This paper proposes a plan-generation-evaluation framework which supports a complete process of such design space exploration. The plan phase constitutes a design space of all possible design alternatives by means of a formally defined representation scheme of attributed AND-OR graph. The generation phase generates a set of candidates by algorithmic pruning of the design space in an attributed AND-OR graph with respect to design requirements as well as architectural constraints. Finally, the evaluation phase measures performance of design candidates in a pruned graph to select a best one. A complete process of cache design is exemplified to show the effectiveness of the proposed framework. | ||||||||||
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