Intel design for manufacturing and evolution of design rules

Clair Webb

doi:10.1117/12.772052

20 March 2008 Intel design for manufacturing and evolution of design rules

Clair Webb

Proceedings Volume 6925, Design for Manufacturability through Design-Process Integration II; 692503 (2008) https://doi.org/10.1117/12.772052
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States

Abstract

The difficult issues in continuing Moore's law with the lack of improvement in lithography resolution are well known.^{1, 2, 3} Design rules have to change and DFM methodology has to continue to improve to enable Moore's law scaling. This paper will discuss our approach to DFM though co-optimization across design and process. The poly layer is used to show how rules have changed to meet patterning requirements and how co-optimization has been used to define the poly design rules. With the introduction and ramp of several products on our 45nm technology, we have shown our ability to meet the goals of Moore's law scaling at high yields in volume manufacturing on a two year cycle.

Citation Download Citation

Clair Webb "Intel design for manufacturing and evolution of design rules", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 692503 (20 March 2008); https://doi.org/10.1117/12.772052

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