Ultra-Low Resistance, Through-Wafer Via (TWV) Technology and Its Applications in Three Dimensional Structures on Silicon

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Copyright (c) 1999 The Japan Society of Applied Physics
, , Citation Hyongsok T. Soh et al 1999 Jpn. J. Appl. Phys. 38 2393 DOI 10.1143/JJAP.38.2393

1347-4065/38/4S/2393

Abstract

This paper presents an ultra-low resistance, high wiring density, through-wafer via (TWV) technology that is compatible with standard silicon wafer processing. Vias as small as 30 µm by 30 µm are fabricated through a 525 µm thick wafer. This results in an aspect ratio for the via that is greater than 17:1. Furthermore, the dc resistance of a single via is less than 50 mΩ. Key fabrication steps, including the silicon dry etch, copper metallization, and photoresist electroplating, are described in detail. As a demonstration of the potential applications of the TWV technology, a novel three dimensional inductor is designed and fabricated. For a 0.9-nH inductor, a quality factor of 18.5 is measured at 800 MHz.

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10.1143/JJAP.38.2393