ABSTRACT
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the confidentiality and integrity algorithms defined for the Universal Mobile Telecommunication System (UMTS) standard. The first proposal is a pipelined design and the second implements an iterative approach. The throughput for these architectures turn out to be higher than the throughput achieved by other proposals.
- 3rd Generation Partnership Program. Document 2: KASUMI Specification. Technical Specification 35.202. Release 5. Version 5.0.0.Google Scholar
- H. Kim, Y. Choi, M. Kim and H. Ryu. Hardware Implementation of the 3GPP KASUMI Crypto Algorithm. In ITC-CSCC-2002 Conference Proceedings. 2002.Google Scholar
- P. Kitsos, M. D. Galanis and O. Koufopavlou. High-Speed Hardware Implementations of the KASUMI Block Cipher. In ISCAS'04 Conference Proceedings. 2004.Google Scholar
- K. Marinis, N. K. Moshopoulos, F. Karoubalis and K. Z. Pekmestzi. On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms, In 4th ISC 2001 Conference Proceedings. 2001. Google ScholarDigital Library
- A. Satoh and S. Morioka. Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. In 5th ISC 2002 Conference Proceedings. 2002. Google ScholarDigital Library
Index Terms
- High performance encryption cores for 3G networks
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