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Power challenges may end the multicore era

Published:01 February 2013Publication History
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Abstract

Starting in 2004, the microprocessor industry has shifted to multicore scaling---increasing the number of cores per die each generation---as its principal strategy for continuing performance growth. Many in the research community believe that this exponential core scaling will continue into the hundreds or thousands of cores per chip, auguring a parallelism revolution in hardware or software. However, while transistor count increases continue at traditional Moore's Law rates, the per-transistor speed and energy efficiency improvements have slowed dramatically. Under these conditions, more cores are only possible if the cores are slower, simpler, or less utilized with each additional technology generation. This paper brings together transistor technology, processor core, and application models to understand whether multicore scaling can sustain the historical exponential performance growth in this energy-limited era. As the number of cores increases, power constraints may prevent powering of all cores at their full speed, requiring a fraction of the cores to be powered off at all times. According to our models, the fraction of these chips that is "dark" may be as much as 50% within three process generations. The low utility of this "dark silicon" may prevent both scaling to higher core counts and ultimately the economic viability of continued silicon scaling. Our results show that core count scaling provides much less performance gain than conventional wisdom suggests. Under (highly) optimistic scaling assumptions---for parallel workloads---multicore scaling provides a 7.9× (23% per year) over ten years. Under more conservative (realistic) assumptions, multicore scaling provides a total performance gain of 3.7× (14% per year) over ten years, and obviously less when sufficiently parallel workloads are unavailable. Without a breakthrough in process technology or microarchitecture, other directions are needed to continue the historical rate of performance improvement.

References

  1. Amdahl, G.M. Validity of the single processor approach to achieving. large-scale computing capabilities. In AFIPS (1967). Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Azizi, O., Mahesri, A., Lee, B.C., Patel, S.J., Horowitz, M. Energy-performance tradeoffs in processor architecture and circuit design: A marginal cost analysis. In ISCA (2010). Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Bhadauria, M., Weaver, V., McKee, S. Understanding PARSEC performance on contemporary CMPs. In IISWC (2009). Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Bienia, C., Kumar, S., Singh, J.P., Li, K. The PARSEC benchmark suite: Characterization and architectural implications. In PACT (2008). Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Borkar, S. The exascale challenge. Keynote at VLSI-DAT (2010).Google ScholarGoogle Scholar
  6. Chakraborty, K. Over-provisioned multicore systems. PhD thesis, University of Wisconsin-Madison (2008). Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Chung, E.S., Milder, P.A., Hoe, J.C., Mai, K. Single-chip heterogeneous computing: Does the future include custom logic, FPGAs, and GPUs? In MICRO (2010). Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Dennard, R.H., Cai, J., Kumar, A. A perspective on today's scaling challenges and possible future directions. Solid-State Electron., 5, 4 (Apr. 2007).Google ScholarGoogle Scholar
  9. Dennard, R.H., Gaensslen, F.H., Rideout, V.L., Bassous, E., LeBlanc, A.R. Design of ion-implanted mosfet's with very small physical dimensions. IEEE J. Solid-State Circuits 9 (Oct. 1974).Google ScholarGoogle ScholarCross RefCross Ref
  10. Guz, Z., Bolotin, E., Keidar, I., Kolodny, A., Mendelson, A., Weiser, U.C. Many-core vs. many-thread machines: Stay away from the valley. IEEE Comput. Archit. Lett. 8 (Jan. 2009). Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Hameed, R., Qadeer, W., Wachs, M., Azizi, O., Solomatnikov, A., Lee, B.C., Richardson, S., Kozyrakis, C., Horowitz, M. Understanding sources of inefficiency in general-purpose chips. In ISCA (2010). Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Hardavellas, N., Ferdman, M., Falsafi, B., Ailamaki, A. Toward dark silicon in servers. IEEE Micro 31, 4 (Jul--Aug. 2011). Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Hempstead, M., Wei, G.Y., Brooks, D. Navigo: An early-stage model to study power-contrained architectures and specialization. In MoBS (2009).Google ScholarGoogle Scholar
  14. Hill, M.D., Marty, M.R. Amdahl's law in the multicore era. Computer 41, 7 (Jul. 2008). Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Ipek, E., Kirman, M., Kirman, N., Martinez, J.F. Core fusion: Accommodating software diversity in chip multiprocessors. In ISCA (2007). Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. ITRS. International technology roadmap for semiconductors, the 2010 update, http://www.itrs.net (2011).Google ScholarGoogle Scholar
  17. Kim, C., Sethumadhavan, S., Govindan, M.S., Ranganathan, N., Gulati, D., Burger, D., Keckler, S.W Composable light weight processors. In MICRO (2007). Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Moore, G.E. Cramming more components onto integrated circuits. Electronics 38, 8 (Apr. 1965).Google ScholarGoogle Scholar
  19. Pollack, F. New microarchitecture challenges in the coming generations of CMOS process technologies. Keynote at MICRO (1999). Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. SPEC. Standard performance evaluation corporation, http://www.spec.org (2011).Google ScholarGoogle Scholar
  21. Suleman, A.M., Mutlu, O., Qureshi, M.K., Patt, Y.N. Accelerating critical section execution with asymmetric multi-core architectures. In ASPLOS (2009). Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Venkatesh, G., Sampson, J., Goulding, N., Garcia, S., Bryksin, V., Lugo-Martinez, J., Swanson, S., Taylor, M.B. Conservation cores: Reducing the energy of mature computations. In ASPLOS (2010). Google ScholarGoogle ScholarDigital LibraryDigital Library

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        cover image Communications of the ACM
        Communications of the ACM  Volume 56, Issue 2
        February 2013
        95 pages
        ISSN:0001-0782
        EISSN:1557-7317
        DOI:10.1145/2408776
        Issue’s Table of Contents

        Copyright © 2013 ACM

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        • Published: 1 February 2013

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