Abstract
The programmability of FPGAs must improve if they are to be part of mainstream computing.
- Auerbach, J., Bacon, D.F., Burcea, I., Cheng, P., Fink, S.J., Rabbah, R. and Shukla, S. A compiler and runtime for heterogeneous computing. In Proceedings of the 49th ACM/EDAC/IEEE Design Automation Conference (2012), 271--276. Google ScholarDigital Library
- Auerbach, J., Bacon, D. F., Cheng, P. and Rabbah, R. Lime: A Java-compatible and synthesizable language for heterogeneous architectures. In Proceedings of the ACM International Conference on Object-oriented Programming Systems Languages and Applications (2010), 89--108. Google ScholarDigital Library
- Aydonat, U., Denisenko, D., Freeman, J., Kinsner, M., Neto, D., Wong, J., Yiannacouras, P. and Singh, D.P. From OpenCL to high-performance hardware on FPGAs. In Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (2012), 531--534.Google Scholar
- Bachrach, J., Richards, B., Vo, H., Lee, Y., Waterman, A., Avidienis, R., Wawrzynek, J. and Asanovic, K. Chisel: Constructing hardware in a scala-embedded language. In Proceedings of the 49th ACM/EDAC/IEEE Design Automation Conference (2012), 1212--1221. Google ScholarDigital Library
- Berkeley Design Technology. An independent evaluation of the AutoESL AutoPilot high-level synthesis tool. Technical Report, 2010.Google Scholar
- Brodtkorb, A.R., Dyken, C., Hagen, T.R., Hjelmervik, J.M. and storaasli, O.O. state-of-the-art in heterogeneous computing. Scientific Programming 18, 1 (2010). Google ScholarDigital Library
- Cardoso, J. and Diniz, P. Compilation Techniques for Reconfigurable Architectures. Springer, 2009. Google ScholarDigital Library
- Coussy, P. and Morawiec, A. High-level Synthesis: From Algorithm to Digital Circuit. Springer, 2008. Google ScholarDigital Library
- Dase, C., Falcon, J. S. and MacCleery, B. Motorcycle control prototyping using an FPGA-based embedded control system. IEEE Control Systems 26, 5 (2006), 17--21.Google Scholar
- Dubach, C., Cheng, P., Rabbah, R., Bacon, D.F., Fink, S.J. Compiling a high-level language for GPUs: (via language support for architectures and compilers). In 33rd SIGPLAN Symposium for Programming Design and Implementation (2012), 1--12. Google ScholarDigital Library
- Edwards, S.A. High-Level Synthesis from the Synchronous Language Esterel. In IEEE/ACM International Workshop on Logic & Synthesis (2002), 401--406.Google Scholar
- Greaves, D. and Singh, S. Designing application-specific circuits with concurrent C# programs. In Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (2010).Google ScholarDigital Library
- Jaaskelainen, P.O., de La Lama, C.S., Huerta, P., Takala, J.H. OpenCL-based design methodology for application-specific processors. Embedded Computer Systems (2010), 223--230.Google Scholar
- Nikhil, R.S. Abstraction in hardware system design. ACM Queue 9, 8 (2011); http://queue.acm.org/detail.cfm?id=2020861. Google ScholarDigital Library
- Owaida, M., Bellas, N., Daloukas, K. and Antonopoulos, C. Synthesis of platform architectures from OpenCL programs. In Field-programmable Custom Computing Machines (2012), 186--193. Google ScholarDigital Library
- Papakonstantinou, A., Karthik, G., Stratton, J. A., Chen, D., Cong, J. and Hwu, W.-M.W. 2009. FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. In Application Specific Processors (2009), 35--42.Google Scholar
- Sharma, S. and Chen, W. Using Model-based design to accelerate FPGA development for automotive applications. The MathWorks, 2009.Google ScholarCross Ref
- Sirowy, S. and Forin, A. Where's the beef? Why FPGAs are so fast. Microsoft Research Technical Report MSR-TR-2008-130, 2008.Google Scholar
- Thomas, D.B., Howes, L., Luk, W. A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. In ACM/SIGDA International Symposium on Field programmable Gate Arrays (2009), 22--24. Google ScholarDigital Library
- WinterGreen Research Inc. Programmable logic IC market shares and forecasts, worldwide, 2010 to 2016. Technical report, 2010.Google Scholar
- Wulf, W.A. and McKee, S.A. Hitting the memory wall: Implications of the obvious. SIGARCH Computer Architecture News 23, 1 (1995), 20--24. Google ScholarDigital Library
- Xilinx. Command line tools user guide. Technical Report UG628 (14.3), 2012.Google Scholar
- Xilinx. 7 series FPGAs overview. Technical Report DS180 (1.13), 2012.Google Scholar
Index Terms
- FPGA programming for the masses
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