Jude A. Rivers
- 1.G.S. Sohi and M. Franklin, "High-Bandwidth Data Memory Systems for Superscalar Processors," Proceedings of ASPLOS-IV, pp. 53-62, April 1991. Google Scholar
Digital Library
- 2.D. Kroft, "Lockup-Free Instruction Fetch/Prefetch Cache Organization," Proceedings oflSCA-8, May 1981. Google ScholarDigital Library
- 3.J.-L. Baer and T.-E Chen, "An Effective On-Chip Preloading Scheme to Reduce Data Access Penalty," Proceedings of Supercomputing '91, Nov. 1991. Google ScholarDigital Library
- 4.D. Callahan, K. Kennedy, and A. Porterfield, "Software Prefetching," Proceedings of ASPLOS-IV, pp. 40-52, April 1991. Google ScholarDigital Library
- 5.T.-E Chen and J.-L. Baer, "Reducing Memory Latency via Non-Blocking and Prefetching Caches," Proceedings of ASPLOS- V, pp. 51-61, April 1992. Google ScholarDigital Library
- 6.G. Tyson, M. Farrens, J. Matthews, and A.R. Pleszkun, "A Modified Approach to Data Cache Management," Proceedings of MICRO-28, pp. 93-103, Dec. 1995. Google ScholarDigital Library
- 7.J.A. Rivers and E.S. Davidson, "Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design," Proceedings of the 1996 ICPP, pp. 154-163, August 1996.Google Scholar
- 8.T. Johnson and W.W. Hwu, "Run-time Adaptive Cache Hierarchy Management via Reference Analysis," Proceedings oflSCA-24, pp. 315-326, June 1997. Google ScholarDigital Library
- 9.N.P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," Proceedings oflSCA-17, pp. 364-373, June 1990. Google ScholarDigital Library
- 10.D. Burger and T. M. Austin, "Evaluating Future Microprocessors: the SimpleScalar Tool Set," Tech. Report #1342, University of Wisconsin, June 1997.Google Scholar
- 11.A. Gonzalez, C. Aliagas, and M. Valero, "A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality," Proceedings oflCS'95, July 1995. Google ScholarDigital Library
- 12.C-C. Lee, I-C. K. Chen, and T.N. Mudge, "The Bi- Mode Branch Predictor," Proceedings of MiCRO-30, pp. 4-13, Dec. 1997. Google ScholarDigital Library
- 13.E. S. Tam, J. A. Rivers, G. S. Tyson, and E. S. Davidson, "mlcache: A Flexible Multi-Lateral Cache Simulator,'' Proceedings of MASCOTS'98, July 1998. Google ScholarDigital Library
Index Terms
- Utilizing reuse information in data cache management
Recommendations
The reuse cache: downsizing the shared last-level cache
MICRO-46: Proceedings of the 46th Annual IEEE/ACM International Symposium on MicroarchitectureOver recent years, a growing body of research has shown that a considerable portion of the shared last-level cache (SLLC) is dead, meaning that the corresponding cache lines are stored but they will not receive any further hits before being replaced. ...
Improving Cache Management Policies Using Dynamic Reuse Distances
MICRO-45: Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on MicroarchitectureCache management policies such as replacement, bypass, or shared cache partitioning have been relying on data reuse behavior to predict the future. This paper proposes a new way to use dynamic reuse distances to further improve such policies. A new ...
Data trace cache: an application specific cache architecture
Special issue: MEDEA'05Benefits of advances in processor technology have long been held hostage to the widening processor-memory gap. Off-chip memory access latency is one of the most critical parameters limiting system performance. Caches have been used as a way of ...
Comments