Boris Murmann
Abstract
In past decades, “Moore’s law”1 has governed the revolution in microelectronics. Through continuous advancements in device and fabrication technology, the industry has maintained exponential progress rates in transistor miniaturization and integration density. As a result, microchips have become cheaper, faster, more complex, and more power efficient.
- 1. Intel, Moore's Law, 2003; http://www.intel.com/ research/silicon/mooreslaw.htm.Google Scholar
- 2. Gray, P. R., et al. Analysis and Design of Analog Integrated Circuits, 4th edition. John Wiley & Sons, New York: NY, 2001. Google ScholarDigital Library
- 3. Pelgrom, M. J. M., et al. Matching properties of MOS transistors. IEEE Journal of Solid-State Circuits 24, 5 (Oct. 1989), 1433-1439.Google ScholarCross Ref
- 4. Lewis, S. H., et al. A 10-b 20-Msample/s analog-to-digital converter, IEEE Journal of Solid-State Circuits 27, 3 (Mar. 1992), 351-358.Google Scholar
- 5. Karanicolas, A. N., et al. A 15-b 1-Msample/s digitally self-calibrated pipeline ADC. IEEE Journal of Solid-State Circuits 28, 12 (Dec. 1993), 1207-1215.Google Scholar
- 6. Murmann, B., and Boser, B. E. A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE Journal Solid-State Circuits 38, 12, (Dec. 2003), 2040-2050.Google ScholarCross Ref
- 7. Jamal, S. M., et al. A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration. IEEE Journal of Solid-State Circuits 37, 12 (Dec. 2002), 1618-1627.Google ScholarCross Ref
- 8. Yu, P. C., et al. A 14 b 40 MSample/s pipelined ADC with DFCA. ISSCC Digest of Technical Papers (Feb. 2001), 136-137.Google Scholar
- 9. Elbornsson, J. Blind estimation and error correction in a CMOS ADC. Proceedings of the ASIC/SOC Conference (Sept. 2000), 124-128.Google ScholarCross Ref
- 10. Blecker, E. B., et al. Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue. IEEE Journal of Solid-State Circuits 38, 6 (June 2003), 1059-1062.Google ScholarCross Ref
- 11. Galton, I. Digital cancellation of D/A converter noise in pipelined A/D converters. IEEE Transactions on Circuits and Systems II 47, 3 (Mar. 2000), 185-196.Google ScholarCross Ref
- 12. Ming, J., and Lewis, S. H. An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration, IEEE Journal of Solid-State Circuits 36, 10 (Oct. 2001) 1489-1497.Google Scholar
- 13. Li, J., and Moon, U.-K. Background calibration techniques for multistage pipelined ADCs with digital redundancy. IEEE Transactions on Circuits and Systems II 50, 9 (Sept. 2003), 531-538.Google Scholar
- 14. Yang, W., et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE Journal of Solid-State Circuits 36, 12 (Dec. 2001) 1931-1936.Google Scholar
- 15. See reference 6.Google Scholar
Index Terms
- Digitally Assisted Analog Integrated Circuits: Closing the gap between analog and digital
Recommendations
Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS
DATE '13: Proceedings of the Conference on Design, Automation and Test in EuropeReliability is one of the major concerns in designing integrated circuits in nanometer CMOS technologies. Problems related to transistor degradation mechanisms like NBTI/PBTI or soft gate breakdown cause time-dependent circuit performance degradation. ...
New Latch-Up Model for Deep Sub-micron Integrated Circuits
DASC '11: Proceedings of the 2011 IEEE Ninth International Conference on Dependable, Autonomic and Secure ComputingThis paper mainly simulated the single event latch-up (SEL) for the CMOS inverter under the 0.18um technology. The SEL of integrated circuit (IC) was also analyzed in detail. The result showed that the parasitic lateral transistors NPN and PNP of NMOS ...
NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits' Life Time
Advances in CMOS technology have made possible the increase of integrated circuit's density, which impacts directly on the circuit's performance. However, technology scaling poses some reliability concerns that directly affect the circuit's lifetime. ...
Comments