Natasa Miskov-Zivanov
Diana Marculescu
ABSTRACT
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we present a symbolic framework based on BDDs and ADDs that enables analysis of combinational circuit reliability from different aspects: output susceptibility to error, influence of individual gates on individual outputs and overall circuit reliability, and the dependence of circuit reliability on glitch duration, amplitude, and input patterns. This is demonstrated by the set of experimental results, which show that the mean output error susceptibility can vary from less than 0.1%, for large circuits and small glitches, to about 30% for very small circuits and large enough glitches. The results obtained with the proposed symbolic framework are within 7% average error and up to 5000X speedup when compared to HSPICE detailed circuit simulation. The framework can be used for selective gate sizing targeting radiation hardening which is done only for gates with error impact exceeding a certain threshold. Using such a technique, soft error rate (SER) can be reduced by 25-67% for various threshold values, when applied to a subset of ISCAS'85 and mcnc'91 benchmarks.
- K. Mohanram and N. A. Touba. Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. In Proc. of International Test Conference (ITC), pp. 893--901, 2003.Google Scholar
Cross Ref
- R. C. Baumann. Soft Errors in Advanced Computer Systems. In IEEE Design and Test of Computers, Vol. 22, Issue 3, 2005. Google ScholarDigital Library
- R. E. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. In IEEE Transaction on Computers, C-35-8, pp. 677--691, August 1986. Google ScholarDigital Library
- R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, F. Somenzi. Algebraic Decision Diagrams and Their Applications. In Proc. of ACM/IEEE International Conference on Computer Aided Design (ICCAD), pp. 188--191, November 1993. Google ScholarDigital Library
- C. Zhao, X. Bai, and S. Dey. A Scalable Soft Spot Analysis Methodology for Noise Effects in Nano-meter Circuits. In Proc. of ACM/IEEE Design Automation Conference (DAC), pp. 894--899, June 2004. Google ScholarDigital Library
- M. Zhang and N. R. Shanbhag. A Soft Error rate Analysis (SERA) Methodology. In Proc. of ACM/IEEE International Conference on Computer Aided Design (ICCAD), pp. 111--118, 2004. Google ScholarDigital Library
- Y. S. Dhillon, A. U. Diril, and A. Chatterjee. Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. In Proc. of Design, Automation and Test in Europe (DATE), pp. 288--293, March 2005. Google ScholarDigital Library
- S. Krishnaswamy, G. F. Viamonte, I. L. Markov, and J. P. Hayes. Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. In Proc. of Design, Automation and Test in Europe (DATE), pp. 282--287, March 2005. Google ScholarDigital Library
- M. Omana, G. Papasso, D. Rossi, and C. Metra. A Model for Transient Fault Propagation in Combinatorial Logic. In Proc. of the 9th IEEE International On-Line Testing Symposium, IOLTS'03, pp. 11--115, July 2003.Google ScholarCross Ref
- B. Zhang, W. Wang, and M. Orshansky. FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. In Proc. of International Symposium on Quality Electronic Design (ISQED), March 2006. Google ScholarDigital Library
- P. Liden, P. Dahlgren, R. Johansson, and J. Karlsson. On Latching Probability of Particle Induced Transients in Combinational Networks. In Proc. of Fault-Tolerant Computing Symposium, pp. 340--349, 1994.Google ScholarCross Ref
- M. P. Baze and S. P. Buchner. Attenuation of Single Event Induced Pulses in CMOS Combinational Logic. In IEEE Transaction on Nuclear Science, Vol. 44, No. 6, pp. 2217--2223, December 1997.Google Scholar
- D. Marculescu, R. Marculescu, and M. Pedram. Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation. In Proc. of IEEE Design, Automation and Test in Europe Conf. (DATE), February 1998. Google ScholarDigital Library
- J. M. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits. Prentice Hall, 2003. Google ScholarDigital Library
- Q. Zhou and K. Mohanram. Cost-Effective Radiation Hardening Technique for Combinational Logic. In Proc. of International Conference on Computer-Aided Design (ICCAD), pp.100--106 , November 2004. Google ScholarDigital Library
- Berkeley Predictive Technology Model (BPTM): http://www-device.eecs.berkeley.edu/~ptm.Google Scholar
- I. Sutherland,B. Sproull and D. Harris. Logical Effort: Designing FastCMOS Circuits. Morgan Kaufmann Publishers, Inc., pp.5--15, 63--73,1999. Google ScholarDigital Library
- N. Miskov-Zivanov and D. Marculescu. Circuit Reliability Analysis Using Symbolic Techniques.To appear in IEEE Transactions on Computer Aided Design (TCAD), 2006. Google ScholarDigital Library
Index Terms
- MARS-C: modeling and reduction of soft errors in combinational circuits
Recommendations
Parallel SER analysis for combinational and sequential standard cell circuits
A parallel SER (soft error rate) evaluation framework ASSET-VLG was developed to analyze the SER of both combinational and sequential standard cell circuits. ASSET-VLG was constructed in practically oriented way: (i) it employs a verilog parser for ...
SER Analysis of Multiple Transient Faults in Combinational Logic
SEEDA-CECNSM '16: Proceedings of the SouthEast European Design Automation, Computer Engineering, Computer Networks and Social Media ConferenceIn the VLSI field, reliability of chips is a major issue and it becomes more significant considering the continuous technology down-scaling. Modern chips are extremely sensitive to various factors such as radiation and, thus, it is crucial to implement ...
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits
ISQED '07: Proceedings of the 8th International Symposium on Quality Electronic DesignDue to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use a symbolic framework based on BDDs and ADDs that enables analysis of ...
Comments