Jürgen Schnerr
ABSTRACT
This paper presents an approach for cycle-accurate simulation of embedded software by integration in an abstract SystemC model. Compared to existing simulation-based approaches, we present a hybrid method that resolves performance issues by combining the advantages of simulation-based and analytical approaches. In a first step, cycle-accurate static execution time analysis is applied at each basic block of a cross-compiled binary program using static processor models. After that, the determined timing information is back-annotated into SystemC for fast simulation of all effects that can not be resolved statically. This allows the consideration of data dependencies during run-time and the incorporation of branch prediction and cache models by efficient source code instrumentation. The major benefit of our approach is that the generated code can be executed very efficiently on the simulation host with approximately 90% of the speed of the untimed software without any code instrumentation.
- K. Albers, F. Bodmann, and F. Slomka. Hierarchical Event Streams and Event Dependency Graphs: A New Computational Model for Embedded Real-Time Systems. In Proceedings of the 18th Euromicro Conference on Real-Time Systems (ECRTS), pages 97--106, 2006. Google Scholar
Digital Library
- C. Cifuentes. Reverse Compilation Techniques. PhD thesis, Queensland University of Technology, 19. Nov. 1994.Google Scholar
- CoWare Inc. CoWare Processor Designer. http://www.coware.com/PDF/products/ProcessorDesigner.pdf.Google Scholar
- A. Donlin. Transaction Level Modeling: Flows and Use Models. In Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 75--80, 2004. Google ScholarDigital Library
- R. Henia, A. Hamann, M. Jersak, R. Racu, K. Richter, and R. Ernst. System Level Performance Analysis - the SymTA/S Approach. IEE Proceedings Computers and Digital Techniques, 152(2):148--166, March 2005.Google Scholar
- IEEE Computer Society. IEEE Standard SystemC® Language Reference Manual, Mar. 2006.Google Scholar
- Infineon Technologies AG. TC10GP Unified 32-bit Microcontroller-DSP - User's Manual, 2000.Google Scholar
- Infineon Technologies Corp. TriCore#8482; 32-bit Unified Processor Core - Volume 1: v1.3 Core Architecture, 2005.Google Scholar
- S. Kraemer, L. Gao, J. Weinstock, R. Leupers, G. Ascheid, and H. Meyr. HySim: A Fast Simulation Framework for Embedded Software Development. In Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 75--80, 2007. Google ScholarDigital Library
- S. Künzli, F. Poletti, L. Benini, and L. Thiele. Combining Simulation and Formal Methods for System-Level Performance Analysis. In Proceedings of the Design, Automation and Test in Europe (DATE) Conference, pages 236--241, 2006. Google ScholarDigital Library
- S.-S. Lim, Y. H. Bae, G. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, S.-M. Moon, and C. S. Kim. An Accurate Worst Case Timing Analysis for RISC Processors. IEEE Transactions on Software Engineering, 21(7):593--604, 1995. Google ScholarDigital Library
- A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H. Meyr, and A. Hoffmann. A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation. In Proceedings of the 39th Design Automation Conference (DAC), pages 22--27, 2002. Google ScholarDigital Library
- OPNET Technologies, Inc. http://www.opnet.com.Google Scholar
- M. Oyamada, F. Wagner, M. Bonaciu, W. Cesário, and A. Jerraya. Software Performance Estimation in MPSoC Design. In Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 38--43, 2007. Google ScholarDigital Library
- K. Richter, M. Jersak, and R. Ernst. A Formal Approach to MpSoC Performance Verification. Computer, 36(4):60--67, 2003. Google ScholarDigital Library
- G. Schirner, A. Gerstlauer, and R. Dömer. Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. In Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 384--389, 2007. Google ScholarDigital Library
- J. Schnerr, O. Bringmann, and W. Rosenstiel. Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs. In Proceedings of the Design, Automation and Test in Europe (DATE) Conference, pages 792--797, 2005. Google ScholarDigital Library
- A. Siebenborn, A. Viehl, O. Bringmann, and W. Rosenstiel. Control-Flow Aware Communication and Conflict Analysis of Parallel Processes. In Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 32--37, 2007. Google ScholarDigital Library
- Synopsys, Inc. Synopsys Virtual Platforms. http://www.synopsys.com/products/designware/virtual_platforms.html.Google Scholar
- L. Thiele, S. Chakraborty, and M. Naedele. Real-time Calculus for Scheduling Hard Real-Time Systems. In IEEE International Symposium on Circuits and Systems (ISCAS), volume 4, pages 101--104, 2000.Google Scholar
- VaST Systems Technology. CoMET®. http://www.vastsystems.com/docs/CoMET_mar2007.pdf.Google Scholar
- A. Viehl, M. Schwarz, O. Bringmann, and W. Rosenstiel. Probabilistic Performance Risk Analysis at System-Level. In Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 185--190, 2007. Google ScholarDigital Library
- A. Viehl, T. Schönwald, O. Bringmann, and W. Rosenstiel. Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design. In Proceedings of the Design, Automation and Test in Europe (DATE) Conference, pages 242--247, 2006. Google ScholarDigital Library
- T. Wild, A. Herkersdorf, and G.-Y. Lee. TAPES -- Trace-Based Architecture Performance Evaluation with SystemC. Design Automation for Embedded Systems, 10(2--3):157--179, Sept. 2005.Google Scholar
Index Terms
- High-performance timing simulation of embedded software
Recommendations
Dominator homomorphism based code matching for source-level simulation of embedded software
CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesisRelating optimized binary code and the source-level statements from which it was created can be challenging if an optimizing compiler was used to create the machine code. Moreover, this relation is crucial if a compiler-optimized program must be ...
Fast and accurate source-level simulation of software timing considering complex code optimizations
DAC '11: Proceedings of the 48th Design Automation ConferenceThis paper presents an approach for accurately estimating the execution time of parallel software components in complex embedded systems. Timing annotations obtained from highly optimized binary code are added to the source code of software components ...
Context-sensitive timing simulation of binary embedded software
CASES '14: Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded SystemsWe present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influenced by the microarchitecture state ...
Comments