Abstract
Phase Change Memory (PCM) is a promising technology for building future main memory systems. A prominent characteristic of PCM is that it has write latency much higher than read latency. Servicing such slow writes causes significant contention for read requests. For our baseline PCM system, the slow writes increase the effective read latency by almost 2X, causing significant performance degradation.
This paper alleviates the problem of slow writes by exploiting the fundamental property of PCM devices that writes are slow only in one direction (SET operation) and are almost as fast as reads in the other direction (RESET operation). Therefore, a write operation to a line in which all memory cells have been SET prior to the write, will incur much lower latency. We propose PreSET, an architectural technique that leverages this property to pro-actively SET all the bits in a given memory line well in advance of the anticipated write to that memory line. Our proposed design initiates a PreSET request for a memory line as soon as that line becomes dirty in the cache, thereby allowing a large window of time for the PreSET operation to complete. Our evaluations show that PreSET is more effective and incurs lower storage overhead than previously proposed write cancellation techniques. We also describe static and dynamic throttling schemes to limit the rate of PreSET operations. Our proposal reduces effective read latency from 982 cycles to 594 cycles and increases system performance by 34%, while improving the energy-delay-product by 25%.
- S. Cho and H. Lee. Flip-n-write: a simple deterministic technique to improve pram write performance, energy and endurance. MICRO 42, pages 347--357, 2009. Google ScholarDigital Library
- L. Crippa, R. Micheloni, I. Motta, and M. Sangalli. Non-volatile memories: Nor vs. nand architectures. In Memories in Wireless Systems, pages 29--53. Springer Berlin Heidelberg, 2008.Google ScholarCross Ref
- C. Lam et al. Block erase for phase change memory. United States Patent Application 20090027950.Google Scholar
- B. Lee et al. Architecting Phase Change Memory as a Scalable DRAM Alternative. In ISCA-36, 2009. Google ScholarDigital Library
- H. Lee et al. Eager writeback - a technique for improving bandwidth utilization. In MICRO-2000. Google ScholarDigital Library
- K.-J. Lee et al. A 90nm 1.8v 512mb diode-switch pram with 266mb/s read throughput. In IEEE Journal of Solid-state Circuits, 2008.Google Scholar
- M. K. Qureshi et al. Scalable high performance main memory system using phase-change memory technology. In ISCA-36, 2009. Google ScholarDigital Library
- M. K. Qureshi et al. Improving read performance of phase change memories via write cancellation and write pausing. In HPCA-16, 2010.Google ScholarCross Ref
- M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali. Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In MICRO-42, pages 14--23, 2009. Google ScholarDigital Library
- M. K. Qureshi, A. Seznec, L. Lastras, and M. Franceschini. Practical and secure pcm systems by online detection of malicious write streams. In HPCA, pages 478--489, 2011. Google ScholarDigital Library
- S. Schechter, G. H. Loh, K. Strauss, and D. Burger. Use ECP, not ECC, for hard failures in resistive memories. In ISCA-37, 2010. Google ScholarDigital Library
- N. H. Seong, D. H. Woo, and H.-H. S. Lee. Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. In ISCA-37, 2010. Google ScholarDigital Library
- A. Snavely, D. M. Tullsen, and G. Voelker. Symbiotic job-scheduling with priorities for a simultaneous multithreading processor. In SIGMETRICS, pages 66--76, 2002. Google ScholarDigital Library
- J. Stuecheli et al. The virtual write queue: coordinating dram and last-level cache policies. ISCA-2010. Google ScholarDigital Library
- J. Tominaga et al. Structure of the Optical Phase Change Memory Alloy, AgVInSbTe, Determined by Optical Spectroscopy and Electron Diffraction,. J. Appl. Phys., 82(7), 1997.Google ScholarCross Ref
- N. Yamada, E. Ohno, K. Nishiuchi, and N. Akahira. Rapid-Phase Transitions of GeTe-Sb2Te3 Pseudobinary Amorphous Thin Films for an Optical Disk Memory. J. Appl. Phys., 69(5), 1991.Google ScholarCross Ref
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang. A durable and energy efficient main memory using phase change memory technology. In ISCA-36, 2009. Google ScholarDigital Library
Index Terms
- PreSET: improving performance of phase change memories by exploiting asymmetry in write times
Recommendations
PreSET: improving performance of phase change memories by exploiting asymmetry in write times
ISCA '12: Proceedings of the 39th Annual International Symposium on Computer ArchitecturePhase Change Memory (PCM) is a promising technology for building future main memory systems. A prominent characteristic of PCM is that it has write latency much higher than read latency. Servicing such slow writes causes significant contention for read ...
Partial-PreSET: Enhancing Lifetime of PCM-Based Main Memory with Fine-Grained SET Operations
Phase change memory (PCM) is one of promising technology to replace DRAM with its attractive features such as zero leakage power and high scalability. In PCM, a SET operation needs much more time than a RESET operation. A typical write request ...
PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)Due to nearly zero leakage power consumption, non-volatile magnetoresistive random access memory (MRAM) is becoming one of the promising candidates for replacing conventional volatile memories (e.g. SRAM and DRAM). In particular, emerging spin-orbit ...
Comments