Muhammad Shafique
Diana Marculescu
ABSTRACT
Technology scaling has resulted in smaller and faster transistors in successive technology generations. However, transistor power consumption no longer scales commensurately with integration density and, consequently, it is projected that in future technology nodes it will only be possible to simultaneously power on a fraction of cores on a multi-core chip in order to stay within the power budget. The part of the chip that is powered off is referred to as dark silicon and brings new challenges as well as opportunities for the design community, particularly in the context of the interaction of dark silicon with thermal, reliability and variability concerns. In this perspectives paper we describe these new challenges and opportunities, and provide preliminary experimental evidence in their support.
- J. Allred et al. Designing for dark silicon: a methodological perspective on energy efficient systems. In Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2012. Google Scholar
Digital Library
- V. Chandra and R. Aitken. Impact of technology and voltage scaling on the soft error susceptibility in nanoscale cmos. In IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008. Google ScholarDigital Library
- M. Choudhury and K. Mohanram. Approximate logic circuits for low overhead, non-intrusive concurrent error detection. In Proceedings of the EDAA Conference on Design Automation and Test in Europe (DATE), 2008. Google ScholarDigital Library
- J. Cong et al. Architecture support for accelerator-rich cmps. In Proceedings of the ACM 49th Annual Design Automation Conference (DAC), 2012. Google ScholarDigital Library
- J. Cong and B. Xiao. Optimization of interconnects between accelerators and shared memories in dark silicon. In Proceedings of the 32nd IEEE/ACM International Conference on Computer-Aided Design, 2013. Google ScholarDigital Library
- R.G. Dreslinski et al. Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits. Proceedings of the IEEE, 98(2):253--266, 2010.Google ScholarCross Ref
- H. Esmaeilzadeh et al. Dark silicon and the end of multicore scaling. In Computer Architecture (ISCA), 2011 38th Annual International Symposium on, pages 365 --376, 2011. Google ScholarDigital Library
- H. Esmaeilzadeh et al. Architecture support for disciplined approximate programming. In Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 301--312, 2012. Google ScholarDigital Library
- H. Esmaeilzadeh et al. Neural acceleration for general-purpose approximate programs. Micro, IEEE, 33(3):16--27, 2013. Google ScholarDigital Library
- Raghunathan et al. Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 39--44, 2013. Google ScholarDigital Library
- N. Goulding-Hotta et al. The greendroid mobile application processor: An architecture for silicon's dark future. Micro, IEEE, 31(2):86--95, 2011. Google ScholarDigital Library
- V. Gupta et al. Impact: Imprecise adders for low-power approximate computing. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pages 409--414, 2011. Google ScholarDigital Library
- J. Han and M. Orshansky. Approximate computing: An emerging paradigm for energy-efficient design. In Proceedings of the 18th IEEE European Test Symposium (ETS), 2013.Google ScholarCross Ref
- V. Hanumaiah et al. Performance optimal online dvfs and task migration techniques for thermally constrained multi-core processors. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 30(11): 1677--1690, 2011. Google ScholarDigital Library
- V. Hanumaiah and S. Vrudhula. Energy-efficient operation of multi-core processors by dvfs, task migration and active cooling. IEEE Transactions on Computers, 99(1):1, 2012. Google ScholarDigital Library
- N. Hardavellas et al. Toward dark silicon in servers. Micro, IEEE, 31(4):6--15, 2011. Google ScholarDigital Library
- J. Henkel et al. Reliable on-chip systems in the nano-era: Lessons learnt and future trends. In Proceedings of the 50th Annual Design Automation Conference, pages 99:1--99:10, 2013. Google ScholarDigital Library
- U.R. Karpuzcu et al. The bubblewrap many-core: popping cores for sequential acceleration. In 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pages 447--458, 2009. Google ScholarDigital Library
- U.R. Karpuzcu et al. Energysmart: Toward energy-efficient manycores for near-threshold computing. In 19th IEEE International Symposium on High Performance Computer Architecture (HPCA), 2013. Google ScholarDigital Library
- F. Kriebel et al. Aser: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era. In DAC, 2014. Google ScholarDigital Library
- P. Kulkarni et al. Trading accuracy for power with an underdesigned multiplier architecture. In Proceedings of the 24th International Conference on VLSI Design (VLSI Design), pages 346--351, 2011. Google ScholarDigital Library
- M. Lyons et al. The accelerator store: A shared memory framework for accelerator-based systems. ACM Trans. Archit. Code Optim., 8(4):48:1--48:22, 2012. Google ScholarDigital Library
- D. Markovic et al. Ultralow-power design in near-threshold region. Proceedings of the IEEE, 98(2):237--252, 2010.Google ScholarCross Ref
- D. Mohapatra et al. Design of voltage-scalable meta-functions for approximate computing. In Proceedings of the Conference on Design, Automation Test in Europe Conference Exhibition (DATE), 2011.Google ScholarCross Ref
- T. Muthukaruppan et al. Hierarchical power management for asymmetric multi-core in dark silicon era. In Proceedings of the 50th Annual Design Automation Conference (DAC), pages 174:1--174:9, 2013. Google ScholarDigital Library
- V. Narayanan and Y. Xie. Reliability concerns in embedded system designs. Computer, 39(1):118--120, 2006. Google ScholarDigital Library
- S. Nussbaum. Amd trinity apu. HotChips '12, 2012.Google Scholar
- I. Paul et al. Cooperative boosting: needy versus greedy power management. SIGARCH Computer Architecture News, 41(3):285--296, 2013. Google ScholarDigital Library
- A. Raghavan et al. Computational sprinting. In Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture (HPCA), pages 1--12, 2012. Google ScholarDigital Library
- E. Rotem et al. Power-management architecture of the intel microarchitecture code-named sandy bridge. IEEE Micro, 32(2):20--27, 2012. Google ScholarDigital Library
- K. Swaminathan et al. Steep-slope devices: From dark to dim silicon. Micro, IEEE, 33(5):50--59, Sept 2013. Google ScholarDigital Library
- M. Taylor. Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse. In Proceedings of the 49th ACM Annual Design Automation Conference (DAC), pages 1131--1136, 2012. Google ScholarDigital Library
- Y. Turakhia et al. Hades: Architectural synthesis for heterogeneous dark silicon chip multi-processors. In Proceedings of the 50th ACM Design Automation Conference (DAC), 2013. Google ScholarDigital Library
- G. Venkatesh et al. Conservation cores: reducing the energy of mature computations. In Proceedings of the 15th Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 205--218, 2010. Google ScholarDigital Library
- G. Venkatesh et al. Qscores: trading dark silicon for scalable energy efficiency with quasi-specific cores. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011. Google ScholarDigital Library
- A.K. Verma et al. Variable latency speculative addition: A new paradigm for arithmetic circuit design. In Proceedings of the Design, Automation and Test in Europe Conference, pages 1250--1255, 2008. Google ScholarDigital Library
- L. Wang and K. Skadron. Implications of the power wall: Dim cores and reconfigurable logic. IEEE Micro, 33(5):40--48, 2013. Google ScholarDigital Library
- The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives
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