- {1} Kristy Andrews and Duane Sand, Migrating a CISC Computer Family onto RISC via Object Translation. Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, October, 1992. Google ScholarDigital Library
- {2} John Hennessy and David Patterson. Computer Organization and Design: The Hardware-Software Interface (Appendix A, by James R. Larus), Morgan Kaufman, 1993. Google ScholarDigital Library
- {3} Robert F. Cmelik, and David Keppel. Shade: A Fast Instruction-Set Simulator for Execution Profiling. Proceedings of the 1994 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems May 1994, pp. 128-137. Google ScholarDigital Library
- {4} Emmett Witchel, Mendel Rosenblum. Embra: Fast and Flexible Machine Simulation. Proceedings of the 1996 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, Philadelphia, 1996. Google ScholarDigital Library
- {5} J. Rowson. Hardware/Software Co-simulation. Proceedings of the 31st ACM/IEEE Design Automation Conference, 1994.Google Scholar
- {6} Vojin Zivojnvic, Steven Tjiang, Heinrich Meyr. Compiled Simulation of Programmable DSP Architectures. Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing, Sakai, Japan.Google Scholar
- {7} S. Sutarwala, P. Paulin, and Y. Kumar. Insulin: An Instruction Set Simulation Environment. Proceedings of CHDL-93, Ottawa, Canada, 1993. Google ScholarDigital Library
- {8} Dawson R. Engler. VCODE: A Portable, Very Fast Dynamic Code Generation System. SIGPLAN Conference on Programming Language Design and Implementation (PLDI '96), Philadelphia, PA, May 1996. Google ScholarDigital Library
- {9} C. W. Fraser, D. R. Hanson A Code Generation Interface for ANSI C. Software-Practice and Experience 21 (9), 963-988, Sep. 1991. Google ScholarDigital Library
Index Terms
- A retargetable, ultra-fast instruction set simulator
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