Eric C. Schnarr
Mark D. Hill
James R. Larus
ABSTRACT
Architectural simulators are essential tools for computer architecture and systems research and development. Simulators, however, are becoming frustratingly slow, because they must now model increasingly complex micro-architectures running realistic workloads. Previously, we developed a technique called fast-forwarding, which applied partial evaluation and mermoization to improve the performance of detailed architectural simulations by as much as an order of magnitude [14].
While writing a detailed processor simulator is difficult, implementing fast-forwarding is even more complex. This paper describes Facile, a domain-specific language for writing detailed, accurate micro-architecture simulators. Architectural descriptions written in Facile can be compiled, using partial evaluation techniques, into fast-forwarding simulators that achieve significant performance improvements with far less programmer effort. Facile and its compiler make this performance-enhancing technique accessible to computer architects.
- 1.Burger, D. and Austin, T. M., "The SimpleScalar Tool Set, Version 2.0," Tech Report #1342,University of Wisconsin- Madison, Department of Computer Sciences, June 1997.Google Scholar
Digital Library
- 2.Chernoff, A., et. al, "FX!32 a profile-directed binary translator," in IEEE Micro 98, March-April 1998, 18 (2)56-64. Google ScholarDigital Library
- 3.Cmelik, B. and Keppel, D., "Shade: A Fast Instructi n-Set Simulator for Execution Profiling," in Proceedings of SIGMETRICS 94, (Nashville TN, May 1994), 128-137. Google ScholarDigital Library
- 4.Consel, C. and Noel, F., "A General Approach for Run-Time Specialization and its Application to C," in Proceedings of POPL96 (St. Petersburgh Beach FL, January 1996), 145-156. Google ScholarDigital Library
- 5.Grant, B., et. al, "An Evaluation of Staged Run-time Optimizations in DyC," in Proceedings of PLDI99 (Atlanta GA, May 1999), 293-304. Google ScholarDigital Library
- 6.Hennessy, J. and Patterson, D., Computer Organization and Design: The Hardware-Software Interface (Appendix A, by James R. Larus), Morgan Kaufman, 1993. Google ScholarDigital Library
- 7.Herrod, S., et. al, "The SimOS Simulation Environment," Computer Systems Laboratory, Stanford University, 1996.Google Scholar
- 8.Jones, N. D., Gomard, C., and Sestoft, P., Partial Evaluation and Automatic Program Generation, Prentice Hall, 1993. Google ScholarDigital Library
- 9.Lee, P. and Leone, M., "Optimizing ML with Run-Time Code Generation," in Proceedings of PLDI96 (Philadelphia PA, May 1996), 137-148. Google ScholarDigital Library
- 10.Magnusson, P. S., et. al, "SimICS/sun4m: A Virtual Workstation," in Proceedings of USENIX98 Technical Conference (New Orleans LA, June 1998). Google ScholarDigital Library
- 11.Pai, V. S., Ranganathan, P., and Adve, S. V., "RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors," in the Workshop on Computer Architecture Education held in conjunction with HPCA97, (San Antonio TX, February 1997).Google Scholar
- 12.Ramsey, N. and Fernandez, M., "The New Jersey Machine- Code Toolkit," in Proceedings of USENIX95 Technical Conference (New Orleans LA, January 1995), 289-302. Google ScholarDigital Library
- 13.Schnarr, E., Applying Programming Language Implementation Techniques To Processor Simulation, Ph.D. Dissertation, University of Wisconsin-Madison, Fall 2000. Google ScholarDigital Library
- 14.Schnarr, E. and Larus, J. R., "Fast Out-Of-Order Processor Simulation Using Memoization," in Proceedings of ASPLOS98 (San Jose CA, October 1998), 283-294. Google ScholarDigital Library
Index Terms
- Facile: a language and compiler for high-performance processor simulators
Recommendations
Facile: a language and compiler for high-performance processor simulators
Architectural simulators are essential tools for computer architecture and systems research and development. Simulators, however, are becoming frustratingly slow, because they must now model increasingly complex micro-architectures running realistic ...
Fast out-of-order processor simulation using memoization
ASPLOS VIII: Proceedings of the eighth international conference on Architectural support for programming languages and operating systemsOur new out-of-order processor simulatol; FastSim, uses two innovations to speed up simulation 8--15 times (vs. Wisconsin SimpleScalar) with no loss in simulation accuracy. First, FastSim uses speculative direct-execution to accelerate the functional ...
Fast out-of-order processor simulation using memoization
Our new out-of-order processor simulatol; FastSim, uses two innovations to speed up simulation 8--15 times (vs. Wisconsin SimpleScalar) with no loss in simulation accuracy. First, FastSim uses speculative direct-execution to accelerate the functional ...
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