Mohammad Sadoghi
Martin Labrecque
Abstract
In this demo, we present fpga-ToPSS (Toronto Publish/Subscribe System Family), an efficient event processing platform for high-frequency and low-latency algorithmic trading. Our event processing platform is built over reconfigurable hardware---FPGAs---to achieve line-rate processing. Furthermore, our event processing engine supports Boolean expression matching with an expressive predicate language that models complex financial strategies to autonomously buy and sell stocks based on real-time financial data.
- M. K. Aguilera, R. E. Strom, D. C. Sturman, M. Astley, and T. D. Chandra. Matching events in a content-based subscription system. In PODC'99. Google Scholar
Digital Library
- J. Corrigan. Updated traffic projections. OPRA, March'07.Google Scholar
- J. Daily. There's millions in those microseconds. The Globe & Mail, 29/1/10.Google Scholar
- F. Fabret, H. A. Jacobsen, F. Llirbat, J. Pereira, K. A. Ross, and D. Shasha. Filtering algorithms and implementation for fast pub/sub systems. SIGMOD'01. Google ScholarDigital Library
- K. Heires. Budgeting for latency: If I shave a microsecond, will I see a 10x profit? Securities Industry, 1/11/10.Google Scholar
- R. Iati. The real story of trading software espionage. TABB Group Perspective, 10/07/09.Google Scholar
- M. Labrecque et al. NetThreads: Programming NetFPGA with threaded software. In NetFPGA Dev. Workshop'09.Google Scholar
- M. Labrecque and J. G. Steffan. Improving pipelined soft processors with multithreading. In FPL'07.Google Scholar
- J. W. Lockwood et al. NetFPGA - an open platform for gigabit-rate network switching and routing. In MSE'07. Google ScholarDigital Library
- R. Martin. Wall street's quest to process data at the speed of light. Information Week, 4/21/07.Google Scholar
- A. Mitra et al. Boosting XML filtering with a scalable FPGA-based architecture. CIDR'09.Google Scholar
- G. W. Morris et al. FPGA accelerated low-latency market data feed processing. IEEE 17th HPI'09. Google ScholarDigital Library
- R. Mueller, J. Teubner, and G. Alonso. Data processing on FPGAs. VLDB'09. Google ScholarDigital Library
- R. Mueller, J. Teubner, and G. Alonso. Streams on wires: a query compiler for FPGAs. VLDB'09. Google ScholarDigital Library
Recommendations
Algorithmic Trading: The Intelligent Trading Systems and Its Impact on Trade Size
Highlights- With rise in algorithmic trading efficiency the trade size decreases significantly.
AbstractFinancial markets have come across a phenomenal adoption of advanced and complex technologies in the pursuit of efficient markets. Algorithmic Trading (AT) is one of the prominent moves in this direction and is widely adopted across ...
Fingerprint image processing acceleration through run-time reconfigurable hardware
To the best of the authors' knowledge, this is the first brief that implements a complete automatic fingerprint-based authentication system (AFAS) application under a dynamically partial self-reconfigurable field-programmable gate array (FPGA). The main ...
C-Based Complex Event Processing on Reconfigurable Hardware
This brief presents an efficient complex event-processing framework, designed to process a large number of sequential events on field-programmable gate arrays (FPGAs). Unlike conventional structured query language based approaches, our approach features ...
Comments