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Synthesis of quantum circuits in Linear Nearest neighbor Model using Positive Davio Lattices

Perkowski Marek (Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA)
Lukac Martin (Graduate School of Information Sciences, Tohoku University, Sendai, Japan)
Shah Dipal (Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA)
Kameyama Michitaka (Graduate School of Information Sciences, Tohoku University, Sendai, Japan)

We present a logic synthesis method based on lattices that realize quantum arrays in One-Dimensional Ion Trap technology. This means that all gates are built from 2x2 quantum primitives that are located only on neighbor qubits in a one-dimensional space (called also vector of qubits or Linear Nearest Neighbor (LNN) architecture). The Logic circuits designed by the proposed method are realized only with 3*3 Toffoli, Feynman and NOT quantum gates and the usage of the commonly used multi-input Toffoli gates is avoided. This realization method of quantum circuits is different from most of reversible circuits synthesis methods from the literature that use only high level quantum cost based on the number of quantum gates. Our synthesis approach applies to both standard and LNN quantum cost models. It leads to entirely new CAD algorithms for circuit synthesis and substantially decreases the quantum cost for LNN quantum circuits. The drawback of synthesizing circuits in the presented LNN architecture is the addition of ancilla qubits.

Keywords: reversible logic synthesis, lattice, Linear Nearest Neighbor model