doiSerbia

Design of efficient coplanar 1-bit comparator circuit in QCA technology

Shiri Ahmadreza (ACECR Institute of Higher Education, Isfahan Branch, Isfahan, Iran)
Rezai Abdalhossein (ACECR Institute of Higher Education, Isfahan Branch, Isfahan, Iran)
Mahmoodian Hamid (ACECR Institute of Higher Education, Isfahan Branch, Isfahan, Iran)

QCA technology is an emerging and promising technology for implementation of digital circuits in nano-scale. The comparator circuits play an important role in digital circuits. In this work, a new and efficient coplanar 1-bit comparator circuit is proposed and evaluated in the QCA technology. The designed coplanar 1-bit QCA comparator circuit is constructed based on majority gate, XNOR gate and inverter gate that are designed carefully. The functionality of the designed coplanar 1-bit QCA comparator circuit is verified by using QCADesigner version 2.0.3. The obtained results indicate that the designed 1-bit QCA comparator circuit requires 0.03 μm2 area and 38 QCA cells. It also has 0.5 clock cycles delay. The comparison demonstrates that the designed QCA comparator circuit provides improvements in comparison with other QCA comparator circuits in terms of effective area, cell count, and delay as well as cost.

Keywords: comparator, quantum-dot cellular automata, high-performance design, coplanar circuit