Welcome to the InfoSci Platform
Reference Hub7
A Simulator for Large-Scale Parallel Computer Architectures

A Simulator for Large-Scale Parallel Computer Architectures

Curtis L. Janssen, Helgi Adalsteinsson, Scott Cranford, Joseph P. Kenny, Ali Pinar, David A. Evensky, Jackson Mayo
Copyright: © 2012 |Pages: 17
ISBN13: 9781466609068|ISBN10: 1466609060|EISBN13: 9781466609075
DOI: 10.4018/978-1-4666-0906-8.ch011
Cite Chapter Cite Chapter

MLA

Janssen, Curtis L., et al. "A Simulator for Large-Scale Parallel Computer Architectures." Technology Integration Advancements in Distributed Systems and Computing, edited by Nik Bessis, IGI Global, 2012, pp. 179-195. https://doi.org/10.4018/978-1-4666-0906-8.ch011

APA

Janssen, C. L., Adalsteinsson, H., Cranford, S., Kenny, J. P., Pinar, A., Evensky, D. A., & Mayo, J. (2012). A Simulator for Large-Scale Parallel Computer Architectures. In N. Bessis (Ed.), Technology Integration Advancements in Distributed Systems and Computing (pp. 179-195). IGI Global. https://doi.org/10.4018/978-1-4666-0906-8.ch011

Chicago

Janssen, Curtis L., et al. "A Simulator for Large-Scale Parallel Computer Architectures." In Technology Integration Advancements in Distributed Systems and Computing, edited by Nik Bessis, 179-195. Hershey, PA: IGI Global, 2012. https://doi.org/10.4018/978-1-4666-0906-8.ch011

Export Reference

Mendeley
Favorite

Abstract

Efficient design of hardware and software for large-scale parallel execution requires detailed understanding of the interactions between the application, computer, and network. The authors have developed a macro-scale simulator (SST/macro) that permits the coarse-grained study of distributed-memory applications. In the presented work, applications using the Message Passing Interface (MPI) are simulated; however, the simulator is designed to allow inclusion of other programming models. The simulator is driven from either a trace file or a skeleton application. Trace files can be either a standard format (Open Trace Format) or a more detailed custom format (DUMPI). The simulator architecture is modular, allowing it to easily be extended with additional network models, trace file formats, and more detailed processor models. This paper describes the design of the simulator, provides performance results, and presents studies showing how application performance is affected by machine characteristics.

Request Access

You do not own this content. Please login to recommend this title to your institution's librarian or purchase it from the IGI Global bookstore.