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Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification

Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification

Liang Guang, Juha Plosila, Jouni Isoaho, Hannu Tenhunen
Copyright: © 2010 |Volume: 1 |Issue: 2 |Pages: 20
ISSN: 1947-3176|EISSN: 1947-3184|EISBN13: 9781609604387|DOI: 10.4018/jertcs.2010040105
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MLA

Guang, Liang, et al. "Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification." IJERTCS vol.1, no.2 2010: pp.86-105. http://doi.org/10.4018/jertcs.2010040105

APA

Guang, L., Plosila, J., Isoaho, J., & Tenhunen, H. (2010). Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 1(2), 86-105. http://doi.org/10.4018/jertcs.2010040105

Chicago

Guang, Liang, et al. "Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification," International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 1, no.2: 86-105. http://doi.org/10.4018/jertcs.2010040105

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Abstract

In this paper, the authors present a formal specification of a novel design paradigm, hierarchical agent monitored SoCs (HAMSOC). The paradigm motivates dynamic monitoring in a hierarchical and distributed manner, with adaptive agents embedded for local and global operations. Formal methods are of essential importance to the development of such a novel and complex platform. As the initial effort, functional specification is indispensable to the non-ambiguous system modeling before potential property verification. The formal specification defines the manner by which the system can be constructed with hierarchical components and the representation of run-time information in modeling entities and every type of the monitoring operations. The syntax follows the standard set theory with additional glossary and notations introduced to facilitate practical SoC design process. A case study of hierarchical monitoring for power management in NoC (Network-on-chip), written with the formal specification, is demonstrated.

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