A novel hardware design for SIFT generation with reduced memory requirement

Eung Sup Kim; Hyuk-Jae Lee

주제분류

...

저널정보

대한전자공학회
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 학술저널
Journal of Semiconductor Technology and Science Vol.13 No.2
2013.4 157 - 169 (13page)

저자정보

Eung Sup Kim (Seoul National University)
Hyuk-Jae Lee (Seoul National University)

이용수
내서재: 0

내서재에 추가
되었습니다. 내서재에서
삭제되었습니다.

초록·키워드

오류제보하기

Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardware based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.

#Terms—SIFT #computer vision #hardware implementation #memory reduction #Gaussian filter bank

Abstract
I. INTRODUCTION
II. SCALE-INVARIANT FEATURE TRANSFORM (SIFT)
III. ANALYSIS OF THE MEMORY REQUIREMENT BY THE PREVIOUS SIFT IMPLEMENTATION
IV. PROPOSED HARDWARE ARCHITECTURE WITH REDUCED MEMORY REQUIREMENT
V. HARDWARE ORGANIZATION FOR COST AND BANDWIDTH REDUCTIONS
VI. EVALUATION
VII. CONCLUSIONS
REFERENCES