- citati u SCIndeksu: 0
- citati u CrossRef-u:[11]
- citati u Google Scholaru:[
 ]
- posete u poslednjih 30 dana:12
- preuzimanja u poslednjih 30 dana:11
|
|
|
2016, vol. 66, br. 4, str. 40-46
|
|
Praktična implementacija DDC za širokopojasni radio-goniometar na FPGA
Practical implementation of digital down conversion for wideband direction finder on FPGA
Keywords: direction finder; wide bandwidth; programmable device; signal conversion
Sažetak
Moderni radio-goniometri su dizajnirani kao senzori za presretanje radio signala u širem trenutnom opsegu. Softverska radio tehnologija nudi mogućnost razvoja arhitekture radio-goniometra sa programabilnom među-frekvencijom, trenutnom širinom opsega i frekvencijskom rezolucijom. U ovom radu, predstavljena je implementacija sinhrone DDC za širokopojasni radio-goniometar na FPGA. DDC se koristi za spuštanje signala sa među-frekvencije u osnovni opseg. Za šire opsege, DDC mora biti implementiran na FPGA, kombinujući tako fleksibilnost opšte namene DSP sa velikom brzinom i malom cenom ASIC implementacije. Predstavljena su merenja i proračuni ulaznih signala sa pet kanala u paraleli na dva FPGA uređaja. U radu su posmatrane i diskutovane prednosti velikih brzina paralelnog računanja uz predstavljanje performansi sistema i dobijenih rezultata.
Abstract
Modern direction finders are designed as sensors for interception of radio signals in wider instantaneous bandwidth. Software radio technology offers ability to develop wideband direction finder architectures with programmable intermediate frequency, instantaneous bandwidth and frequency resolution. In this paper implementation of synchronous digital down conversions (DDCs) for wideband direction finder on FPGA is presented. DDCs are used to down convert signal from intermediate frequency (IF) to baseband. For wider bandwidth DDCs need to be implemented on FPGA which combines the flexibility of a general-purpose DSP plus the speed, density, and low cost of an application-specific integrated circuit (ASIC) implementation. Measurements and computation of input signals from five channels in parallel on two FPGA devices is presented. Benefits of high speed parallel computing have been observed and discussed in this work. System performance and measured results are briefly presented in paper.
|
|
|
|
Reference
|
|
|
Angsuman, R. (2004) FPGA-based applications for software radio. RF Design Magazine, pp. 24-35
|
|
|
Okiljević, P., Pokrajac, I., Jelušić, D. (2012) Optimizing CIC and FIR filter’s coefficients in GC4016 DDC chain. u: 20. Telecommunications Forum (TELFOR 2012), 20-22. November 2012, Belgrade, Serbia, IEEE, pp. 756-759
|
|
2  
|
Pokrajac, I., Okiljević, P., Vučić, D. (2012) Fusion of multiple estimation of emitter positions. Scientific Technical Review, vol. 62, br. 3-4, str. 55-61
|
|
|
Tuncer, T.E., Friedlander, B. (2009) Classical and modern direction- of-arrival estimation. USA: Academic Press
|
|
|
|
|