Fabrication and Characterization of Metal–Ferroelectric–Insulator–Semiconductor Capacitor Structure with Ferroelectric (Bi,Pr)(Fe,Mn)O₃ Thin Films

(Bi,Pr)(Fe,Mn)O₃ (BPFM) thin films were deposited on SiO₂/Si substrates by a chemical solution deposition method, resulting in the metal–ferroelectric–insulator–semiconductor (MFIS) capacitor structure. Polycrystalline BPFM films were grown on the substrate without impurity phases. Comparing with the capacitance vs voltage (C–V) curves of the MFIS capacitor structures with and without the BPFM self-barrier layer, the BPFM self-barrier layer suppress the formation of charge trap sites in the interface between the BPFM and SiO₂ layers of the present structure, resulting in the prepared MFIS capacitor structure showing a clockwise C–V hysteresis behavior due to remnant polarization of the BPFM layer. The memory window width in the C–V curve was approximately 0.5 V for the bias voltage sweep from -20 to +20 V.