AlGaN/GaN high-electron-mobility transistor technology for high-voltage and low-on-resistance operation

The AlGaN/GaN heterostructures were grown by metal–organic chemical vapor deposition (MOCVD) on 2-in. free-standing GaN substrates. The GaN substrate, prepared by hydride vapor phase epitaxy (HVPE), was doped with Fe with a doping concentration of about 1 × 10¹⁸ cm⁻³ to ensure a semi-insulating property. The threading dislocation density of the starting GaN substrate was nominally 10⁶ cm⁻². The epitaxial structure consists of a 25-nm-thick AlGaN barrier layer, a 900-nm-thick undoped GaN channel layer, and a 300-nm-thick Fe-doped GaN buffer layer. The Al content in the AlGaN barrier layer was 0.2.

Figure 1 shows the simplified schematic of the fabrication process and subsequent device structure. The device fabrication started with mesa isolation using BCl₃/Cl₂-based ICP reactive ion etching (RIE). To study the effect of mesa isolation on breakdown characteristics, the mesa etching depth was varied from 200 to 1400 nm. Then, source and drain ohmic contacts were formed by evaporating Ti/Al/Mo/Au metal stacks, followed by rapid thermal annealing at 850 °C for 30 s in an N₂ atmosphere. Ni/Au was then deposited as Schottky gate electrodes. Finally, the devices were passivated with a 150 nm sputter-deposited SiN film. The gate length (L_g), gate width (W_g), and gate-to-source distance (L_gs) were fixed at 3, 100, and 3 µm, respectively, while the gate-to-drain distance (L_gd) was varied from 5 to 200 µm. Figure 2 shows schematic diagrams of AlGaN/GaN HEMTs fabricated on a semi-insulating GaN substrate with mesa depths of 200, 1000, and 1400 nm, where the mesa surfaces are located on the undoped GaN channel, on the Fe-doped GaN buffer layer, and on the semi-insulating GaN substrate, respectively.

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Figure 3 shows the output and transfer current–voltage characteristics (I_d–V_ds and I_d–V_gs) of the AlGaN/GaN HEMT fabricated on a semi-insulating GaN substrate with a mesa depth of 200 nm and L_gd = 10 µm. The device exhibited a maximum drain current of 0.4 A/mm, a threshold voltage of −2.9 V, an on-state resistance of 10 Ω-mm, an on/off current ratio of 10⁹, and a subthreshold swing of 73 mV/dec. Overall DC characteristics were almost the same as those for the HEMT fabricated on a SiC substrate with essentially the same epitaxial structures and device geometry.

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Figure 4 shows the off-state breakdown voltage as a function of L_gd for AlGaN/GaN HEMTs with a mesa depth of 200 nm. The off-state breakdown voltage, defined at a drain current of 1 mA/mm, exhibited a linear increase with the increase in L_gd and reached 3.8 kV at L_gd = 60 µm, beyond which the device showed saturation in the breakdown voltage at approximately 4 kV. From the gradient in the linear region of this plot, the effective breakdown electric field was derived to be 0.6 MV/cm, which is slightly lower than those reported in AlGaN/GaN HEMTs fabricated on foreign substrates such as Si,^{9–11,13–15,17,18)} sapphire,^2–5) and SiC.^1,8,12,16) Careful observations revealed that catastrophic breakdown was dominant in the linear region up to L_gd = 60 µm, while the breakdown voltage was determined by the increased leakage current in the saturation region beyond L_gd = 60 µm. These results suggest the presence of parasitic leakage paths for devices with a mesa depth of 200 nm.

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A question therefore arises whether the additional leakage paths originate from the intrinsic (in the mesa isolation region) or extrinsic (outside the mesa isolation region) part of the HEMT device. To address this issue, devices with deeper mesa isolation etching were subjected to similar breakdown voltage measurements in terms of L_gd. Figure 5(a) shows the off-state breakdown voltage as a function of L_gd for AlGaN/GaN HEMTs with mesa depths of 1000 and 1400 nm. For devices with a mesa depth of 1000 nm, where the surface of mesa isolation is located on the Fe-doped GaN buffer layer, the off-state breakdown voltage was linearly increased up to L_gd = 60 µm and then became saturated at approximately 4 kV. The total breakdown behavior for the mesa depth of 1000 nm was essentially the same as that for the mesa depth of 200 nm, indicating that the presence of a 900 nm GaN channel layer in the mesa area does not induce additional leakage current components. Meanwhile, an entirely different breakdown behavior was observed for the device with a mesa depth of 1400 nm, where the surface of the mesa isolation is located on the semi-insulating GaN substrate. The 1400 nm mesa-etched devices demonstrated an almost linear increase in the breakdown voltage up to a measurement setup limit of 5 kV. From the slope of the dependence, an effective lateral breakdown field of 1 MV/cm was extracted. This increase in the breakdown field is primarily due to the removal of the Fe-doped GaN buffer layer, suggesting that the presence of the GaN buffer layer permits some premature breakdown and/or flow of non-negligible leakage current in the extrinsic part of the device, as illustrated in Fig. 5(b).

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To understand the effect of mesa etching depth in more detail, two-terminal I–V characteristics were measured between ohmic contact electrodes formed on the same AlGaN/GaN heterostructures. Each ohmic electrode, having a square shape with a width of 100 µm, was mesa isolated by varying the mesa depth from 200 to 5000 nm. Breakdown characteristics were measured between ohmic electrodes separated with distances of 20 and 35 µm as a function of mesa etching depth. As shown in Fig. 6, a steplike increase in breakdown voltage is clearly observed in the mesa depth region between 1000 and 1400 nm. The breakdown voltage became almost constant at mesa depths larger than 1400 nm, where the GaN buffer layer was completely etched away. These results confirm that a higher resistivity in the GaN buffer layer is of substantial importance to achieve better breakdown characteristics in an AlGaN/GaN HEMT structure on a free-standing GaN substrate.

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From a series of breakdown measurements for AlGaN/GaN HEMTs fabricated on a semi-insulating GaN substrate with different mesa etching depths, it was found that the highest available breakdown voltage seemed to be restricted by the breakdown and/or the leakage current in a semi-insulating GaN substrate under high applied electric field conditions. To confirm this limitation, the breakdown characteristics were measured between ohmic contact electrodes, which were directly formed on a GaN substrate. Measurements were made on a HVPE-grown free-standing GaN substrate with an Fe doping concentration of 1 × 10¹⁸ or 9 × 10¹⁹ cm⁻³. Results are shown in Fig. 7, where measured breakdown voltages are plotted as a function of ohmic-to-ohmic distance varied from 4 to 25 µm. For both semi-insulating GaN substrates, the breakdown voltage increased linearly with the increase in the ohmic-to-ohmic distance. Note that an effective lateral breakdown field of as high as 2 MV/cm was achieved for the heavily Fe-doped GaN substrate (9 × 10¹⁹ cm⁻³). This value is, to the best of the authors' knowledge, the highest effective breakdown field ever recorded on the horizontal GaN devices. These results strongly suggest that a higher lateral breakdown field may be achievable by further increasing the resistivity of a semi-insulating GaN substrate through the reduction of the background donor concentration and/or the defect density in a GaN substrate.

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One might think that SiC or sapphire would be more preferable as a starting substrate to achieve higher values in the effective lateral breakdown field in AlGaN/GaN HEMTs because the material has more perfect semi-insulating properties. However, this is not true because more complicated and thicker buffer layers are usually necessary to grow high-quality GaN-based heterostructures. Only a free-standing GaN substrate can permit the growth of very thin buffer GaN layers with controlled high-resistivity properties, which are of particular importance to suppress parasitic leakage current and/or premature breakdown.

Current collapse is another major hurdle that needs to be properly addressed before the wide-scale adoption of AlGaN/GaN HEMTs for power electronics. This section is devoted to summarizing our recent efforts in exploring alternative solutions towards the suppression of current collapse, such as high-pressure water vapor annealing (HPWVA), oxygen (O₂) plasma treatment, introduction of FP, and using 3DFP structures. For gauging the effectiveness of these different approaches to current collapse, the performance of each prototype device employing the above-mentioned schemes was compared with that of a reference device fabricated on the same substrate. This is to avoid process-specific variations in contact resistances and other relevant device parameters that may mask the effect of the different approaches on device performance being measured. Reference devices were fabricated using the same process shown in Fig. 1. For each prototype device employing one of the above-mentioned schemes, additional steps were inserted into the fabrication process, as will be discussed later accordingly. For the purpose of current collapse evaluation, devices were fabricated using an Al_0.2Ga_0.8N/GaN heterostructure grown on a 4H-SiC substrate by MOCVD. The epitaxial structure consists of a 25-nm-thick AlGaN barrier layer, a 500-nm-thick undoped GaN channel layer, and an AlN nucleation layer (NL). The AlN NL facilitates high-quality GaN heteroepitaxy by accommodating the lattice mismatch between the GaN layer and the underlying SiC substrate. Unless otherwise specified, for all devices, L_gs, L_g, L_gd, and W_g were 3, 3, 10, and 100 µm, respectively.

Figure 8 outlines the important details of the current collapse evaluation method performed on the devices. As given in Fig. 8(a), a drain bias voltage (V_DD) provided by a power supply (Texio PA600-0.1B) was used in series with a load resistance (R_L), while a train of gate pulses from a pulse generator (Iwatsu DG 8000) was applied to the gate. The values of V_DD and R_L were appropriately chosen so that the resulting load line intersects the I_d–V_ds curve at a point below 1/4 of the maximum drain current. This ensured that R_on being measured was within the linear region. During the off-state, V_DD supplies the off-state drain voltage stress V_{ds_off}. For mimicking a typical operation under which devices in power switching circuits are subjected, values of the gate voltage (V_gs) alternating between −5 V (off-state) and +1 V (on-state) were applied to the gate terminal as shown in Fig. 8(b).

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For brevity, we first define t_on as a preselected fixed time interval following the rising edge of the gate pulse, during which the device is in the "on" state as illustrated in Fig. 8(b). In other words, t_on is the elapsed time after switching the device from off- to on-state. After every t_on, the corresponding V_ds(t_on) and I_d(t_on) were recorded using an oscilloscope (LeCroy WaveRunner 204Xi-A) and used to compute the dynamic R_on as illustrated in Fig. 8(c). For representing current collapse quantitatively, we used the normalized dynamic R_on (NDR), which is defined as the ratio of dynamic R_on to static R_on. A higher NDR indicates a higher degree of current collapse. Using the electrical circuit given in Fig. 8(a), we can then monitor how the NDR of the devices evolves with the variation in either V_{ds_off} (method 1) or t_on (method 2) for current collapse evaluation. The dependence of NDR on t_on can also be used to estimate the energy levels of the traps responsible for the current collapse as discussed below.

The general expression for R_on is given by the following relationship:

$$\begin{equation} R_{\text{on}}=2R_{\text{c}}+R_{\text{s}}+R_{\text{ch}}+R_{\text{d}}, \end{equation} \tag{ 1 }$$

where R_c, R_s, R_ch, and R_d represent contact resistance, source access resistance, channel resistance, and drain access resistance, respectively. According to the model by Vetury et al.,⁴⁶⁾ current collapse is due to the trapping of injected electrons on the drain side of the gate edge during the off-state, which eventually depletes the underlying 2DEG in this portion of the gate-to-drain access region, consequently increasing the dynamic R_on, i.e., current collapse. After switching the device from off- to on-state, the drain access resistance transient R_d(t) can be mathematically given by

$$\begin{equation} R_{\text{d}}(t)=\frac{1}{en_{\text{s}}(t)\mu}\frac{L_{\text{gd}}}{W_{\text{g}}}, \end{equation} \tag{ 2 }$$

where

$$\begin{equation} n_{\text{s}}(t)=n_{\text{s}}(\infty)-\sum_{i}^{N}\Delta n_{\text{si}}\exp\left(-\frac{t}{\tau_{i}}\right). \end{equation} \tag{ 3 }$$

Here, t is the elapsed time after switching the device from off- to on-state. n_s(t) and n_s(∞) represent the effective drain access region 2DEG density at time t and t = ∞ (static), respectively. As given by Eq. (3), the difference in n_s(∞) and n_s(t) can be given by the sum of pure exponential terms, where Δn_si represents the effective sheet density of trapped electrons in the ith trap with a corresponding emission time constant τ_i immediately prior to switching the device to the on-state. As t increases, the sum of the exponential terms representing the effective density of trapped electrons approaches zero. Substituting Eq. (3) into Eq. (2) yields

$$\begin{equation} R_{\text{d}}(t)=\frac{L_{\text{gd}}}{W_{\text{g}}e\mu}\left[\frac{1}{n_{\text{s}}(\infty)-\displaystyle\sum_{i}^{N}\Delta n_{\text{si}}\exp(-t/\tau_{i})}\right]. \end{equation} \tag{ 4 }$$

Applying Taylor series approximation on the expression inside the parenthesis, one can easily obtain

$$\begin{equation} R_{\text{d}}(t)=\frac{L_{\text{gd}}}{W_{\text{g}}e\mu n_{\text{s}}(\infty)}\left[1+\sum_{i}^{N}\frac{\Delta n_{\text{si}}\exp(-t/\tau_{i})}{n_{\text{s}}(\infty)}\right]. \end{equation} \tag{ 5 }$$

Using Eq. (5), we can rewrite Eq. (1) into

$$\begin{align} R_{\text{on}}(t)&=2R_{\text{c}}+R_{\text{s}}+R_{\text{ch}}\\ &\quad+R_{\text{d}}(\infty)\left[1+\sum_{i}^{N}\frac{\Delta n_{\text{si}}\exp(-t/\tau_{i})}{n_{\text{s}}(\infty)}\right], \end{align} \tag{ 6 }$$

where

$$\begin{equation} R_{\text{d}}(\infty)=\frac{L_{\text{gd}}}{W_{\text{g}}e\mu n_{\text{s}}(\infty)}. \end{equation} \tag{ 7 }$$

From the definition of NDR, we can finally obtain

$$\begin{equation} \mathrm{NDR}\equiv\frac{R_{\text{on}}(t)}{R_{\text{on}}(\infty)}=1+\sum_{i}^{N}\alpha_{i}\exp\left(-\frac{t}{\tau_{i}}\right), \end{equation} \tag{ 8 }$$

where α_i is the fractional contribution of the ith component and is given by

$$\begin{equation} \alpha_{i}=\frac{R_{\text{d}}(\infty)}{R_{\text{on}}(\infty)}\frac{\Delta n_{\text{si}}}{n_{\text{s}}(\infty)}. \end{equation} \tag{ 9 }$$

Note that α_i is directly proportional to Δn_si, which is the effective sheet density of trapped electrons in the ith trap immediately prior to switching the device from off- to on-state, and is related to the ith trap density itself. In addition, it is worth mentioning that Eq. (8) is very similar in form to the transient drain current expression proposed by Joh and del Alamo.⁵⁹⁾

The experimentally measured t_on dependence of NDR can be fitted with Eq. (8) to extract the τ_i of the ith trap level, from which the corresponding (E_C − E_t) energy value can be obtained using the Shockley–Read–Hall (SRH) statistics relationship

$$\begin{equation} \tau_{i}=\frac{1}{v_{\text{th}}\sigma_{\text{n}}N_{\text{C}}}\exp(E_{\text{C}}-E_{\text{t}}). \end{equation} \tag{ 10 }$$

Here, v_th is the electron thermal velocity, σ_n is the capture cross section, and N_C is the effective density of states at the conduction band edge.

There is somewhat a general agreement in the literature that current collapse is predominantly, if not solely, due to trapping on the AlGaN surface. Needless to say, one of the earliest proven approaches against current collapse is AlGaN surface passivation.⁴⁷⁾ Because of the high sensitivity of current collapse to AlGaN surface condition, different prepassivation treatment methods should also be explored as alternative solutions. Sameshima and co-workers were the first to demonstrate the applicability of high-pressure water vapor annealing (HPWVA) to semiconductor process technologies.^60,61) They reported improved properties of SiO₂ films and SiO₂/Si interfaces subjected to HPWVA. It was also found by Punchaipetch et al.⁶²⁾ that HPWVA was able to raise the quality of hafnium silicate (HfSi_xO_y), which is one of the high-κ gate dielectric materials used in modern semiconductor devices. Recently, Yoshitsugu et al.⁶³⁾ have demonstrated the effectiveness of HPWVA in improving the quality of Al₂O₃ gate dielectric in n-GaN MOS capacitors. Following these pioneering works, a significant reduction in current collapse was also achieved in AlGaN/GaN HEMTs using HPWVA.⁶⁴⁾ The HPWVA process was carried out prior to the SiN passivation step. Devices to be subjected to HPWVA were initially set in a sealed chamber. Together with the devices, a predetermined volume of pure water was placed inside the chamber. This volume of water corresponded to the desired pressure at a given setting temperature. A water vapor pressure of 0.5 MPa was used in this work. The chamber was then sealed and heated to a desired annealing temperature for a particular length of time, and then allowed to cool naturally. With a fixed annealing time of 30 min, three different HPWVA conditions corresponding to annealing temperatures of 200, 300, and 400 °C were used.

Figure 9(a) shows the measured NDR as a function of t_on of the reference and HPWVA-processed devices. As expected, NDR decreased with increasing t_on for all devices. This is because a longer t_on allowed more time for the emission of trapped electrons, resulting in a greater recovery of dynamic R_on. More importantly, NDR decreased with increasing annealing temperature for all HPWVA-processed devices as compared with the reference device, suggesting the efficacy of HPWVA in alleviating current collapse.

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By fitting the measured NDR–t_on curve with Eq. (8) by the least-squares method, six deep level traps were detected from the reference device, as illustrated in Fig. 9(b). In this figure, extracted exponential terms are plotted by dashed curves, each of which represents a particular trap level. On the other hand, only two levels were detected from the 400 °C HPWVA-processed device. Table I summarizes the extracted values of τ_i and α_i of these trap levels. Assuming v_th of 2.6 × 10⁷ cm/s, σ_n of 1.0 × 10⁻¹⁵ cm², and N_C of 2.2 × 10¹⁸ cm⁻³, the trap energy level (E_C − E_t) values given in the fourth column of Table I were obtained using Eq. (10).

The (E_C − E_t) values ranged from 0.28 to 0.64 eV and from 0.28 to 0.37 eV for the reference and the HPWVA-processed device, respectively. The corresponding α_i of traps after HPWVA were orders of magnitude lower than those of the reference device. Subsequent X-ray photoelectron spectroscopy (XPS) analyses revealed the chemical blue shift of Ga Auger LMM signals from the HPWVA-processed AlGaN surface relative to those of the reference sample, suggesting the formation of the surface oxide layer of Ga₂O₃ and possibly interfacial Ga₂O sub-oxide, which was reported to be essential for achieving low defect density in III–V surfaces.^65–68) On a final note, HPWVA is considered to promote oxygen incorporation, which leads to the formation of surface oxide suitable for device passivation, occupation of near-surface nitrogen vacancies, and termination of unbounded near-surface Ga and Al atoms.¹⁶⁾ All of these effectively decreased the number of surface states that trap carriers, leading to a highly reduced current collapse.

Various gas-plasma treatments of AlGaN surface were reported to be effective in mitigating current collapse.^69–71) Recently, a significant reduction in current collapse has been demonstrated for O₂ plasma-treated AlGaN/GaN HEMTs as evidenced by highly reduced NDR in these devices over that of a reference device.⁷²⁾ The AlGaN surface of the devices was exposed to O₂ plasma with an RF power of 100 W and an exposure time of 60 s. This was carried out prior to a SiN passivation step of the fabrication process shown in Fig. 1. Meanwhile, there were also reports that an epitaxial GaN cap layer was capable of reducing current collapse.^73–77) Aware of these reports, we also applied O₂ plasma surface treatment to the fabrication of AlGaN/GaN HEMTs having a GaN cap layer. Four different devices with the following features were fabricated: (1) without GaN cap and without O₂ plasma treatment as reference device; (2) without GaN cap and with O₂ plasma treatment; (3) with GaN cap and without O₂ plasma treatment; and (4) with GaN cap and with O₂ plasma treatment. Figure 10 presents the NDR values of the four devices as a function of t_on. Careful investigation of the resulting NDR–t_on curves led to the following two important conclusions: (1) O₂ plasma treatment was more effective than the GaN cap in suppressing current collapse and (2) the GaN cap layer approach was redundant and insignificant to current collapse mitigation when used in combination with O₂ plasma treatment. These key findings suggest that by using only O₂ plasma treatment, one can avoid the problems associated with surface GaN layers, such as increased leakage current and difficulty in obtaining good ohmic contacts.^76,77) Following the fitting procedure of NDR–t_on curves and analysis using SRH statistics, the characteristic τ_i's and the equivalent energy levels of traps present in each device were extracted. The results, summarized in Table II, suggest that the O₂ plasma treatment is more effective than the GaN cap approach because the O₂ plasma treatment leads to a significant reduction in surface trap densities, as suggested by its smaller α_i values. Moreover, it also completely eliminated two of the deepest trap levels located at ∼0.62 and ∼0.67 eV. The GaN cap approach, on the other hand, only eliminated the deepest trap level at ∼0.67 eV. The more pronounced current collapse suppression in O₂-plasma-treated devices, with or without GaN cap, was likely due to the formation of surface oxide, the termination of the near-surface Ga and Al atoms, and the occupation of nitrogen vacancies.¹⁶⁾ These suppositions were supported by data from XPS investigations, which indicated oxygen atom incorporation and the subsequent formation of a 2-nm-thick surface oxide after O₂ plasma exposure.

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The use of the FP structure in AlGaN/GaN HEMTs dates back from the early 2000s. Ando et al. were the first to demonstrate high-voltage and high-efficiency microwave power performance using gate-FP in AlGaN/GaN HEMTs.⁵²⁾ They already noticed experimentally the importance of gate-FP in reducing current collapse as well as in improving device breakdown characteristics. Using the same FP technology, Okamoto et al. achieved the first over 200 W one-chip microwave power operation at 2 GHz.⁵³⁾ Since then, a number of papers have been published reporting that FP in AlGaN/GaN HEMTs is effective in enhancing device breakdown voltages.^54–57) The FP structure redistributes the electric field profile along the drain access region, leading to a reduced electric field peak near the drain side of the gate edge and eventual breakdown voltage enhancement. Therefore, in principle, current collapse, which is considered to be due to trapping on the AlGaN surface of injected electrons from the metal gate, should also be reduced by the introduction of FP. Saito et al. reported improved collapse behaviors of the dual-FP HEMT over the single-FP device and attributed this difference to the leveled electric field distribution in the gate-to-drain region under off-state high-voltage biasing conditions.⁵⁵⁾

The beneficial FP effects on current collapse were experimentally verified not only during the off-state but also during the on-state in the power switching operation. Hasan et al. fabricated an AlGaN/GaN HEMT with a gate-FP, as illustrated in Fig. 11, and measured the dynamic R_on as a function of on-state V_gs from −1 to +1 V.⁵⁸⁾ As clearly shown in Fig. 12, applying a more positive on-state V_gs resulted in the greater reduction of current collapse for the gate-FP device, but no such gate-bias dependence was observed for the standard HEMT without FP. Note that with decreasing on-state V_gs to −1 V, the NDR of the gate-FP HEMT approaches that for the HEMT without FP. This result revealed that the gate-FP has an important effect on current collapse during the on-state. Through the field-effect charge control of the gate-FP on channel electrons, the positively biased gate-FP is particularly effective in instantly recovering the partial depletion of channel electrons, which was caused by electron trapping during the off-state. Such beneficial effect during the on-state is peculiar to the gate-FP and would not be expected for the source-FP.

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Aiming for a true "collapse-free" operation, attempts of combining different approaches against current collapse were also reported. It was suggested that using simultaneously two different approaches in mitigating current collapse did not necessarily guarantee a cumulative effect.⁷²⁾ To put it explicitly, it was found that the GaN cap layer contributed no further reduction in current collapse in the devices already subjected to O₂ plasma treatment. Another report described a systematic investigation of the combined effect of O₂ plasma treatment and FP structure on current collapse.⁷⁸⁾ For that purpose, four different devices with the following features were fabricated: (1) reference, (2) with FP, (3) with O₂ plasma treatment, and (4) with FP and with O₂ plasma treatment, referred as HEMT A, B, C, and D, respectively. For the O₂-plasma-treated devices, the AlGaN surface was subjected to O₂ plasma treatment using the same plasma power of 100 W and exposure time of 60 s before SiN passivation. Figure 13 shows NDR as a function of V_{ds_off}. As expected, all devices exhibited the increasing trend of current collapse with increasing V_{ds_off}. It was found that the O₂ plasma treatment approach led to a stronger degree of current collapse suppression over the FP approach. Interestingly, the device with both FP and O₂ plasma treatment showed the lowest degree of current collapse, indicating the cumulative effect of FP and O₂ plasma treatment approaches in weakening current collapse. Asubar et al. explained that the effectiveness of the combined schemes was due to the fact that each scheme dealt with current collapse in a different way.⁷⁸⁾ While O₂ plasma treatment reduced or eliminated surface trap densities responsible for current collapse, the FP structure modified the driving forces directly affecting the trapping and detrapping processes connected with current collapse.^53–56)

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The multimesa-channel (MMC) AlGaN/GaN HEMT, schematically illustrated in Fig. 14, was an interesting structure-based approach of mitigating current collapse. The MMC device was fabricated by etching periodic trenches to form multiple mesas under the metal gate,^79,80) hence the name multimesa channel. Each mesa channel, formed by electron beam lithography, was designed to have a width (W_top) of less than 100 nm. The resulting structure facilitated the modulation of 2DEG not only through the top but also through the sidewalls, improving the device gate control over the drain current.⁸¹⁾ Ohi et al. found that the device was less sensitive to changes in drain access resistance brought about by increasing L_GD or trapping, and therefore less susceptible to current collapse.^82,83) They argued that this was due to the much higher resistance of the mesa channel compared with that of the drain access region. This device, however, had a drawback of decreased net drain current per chip size due to the etching of active sections of the channel to form the trenches.

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As discussed in the previous section, field-plate technology is well recognized as a powerful tool to achieve reduced current collapse without inducing any adverse effects in the device DC characteristics. However, a true collapse-free operation has not yet been established. Since the gate-FP in AlGaN/GaN HEMTs is proven effective to achieve significant current collapse reduction, enhancing the charge-control ability of the gate-FP would help maximize the efficiency of current collapse suppression. Meanwhile, it was verified that the addition of the lateral field effect in the configuration of the multimesa channel was effective in reducing current collapse. However, the removed section in the channel region reduced the effective active device width, leading to the decrease in the total drain current. This means eventual degradation in the on-resistance per chip size, which is of course detrimental for power device applications.

A new type of field plate device was developed with a view of intensifying the current collapse mitigating effect by FP. The structure is schematically illustrated in Fig. 15, in which multiple grooves were selectively fabricated in the field-plate area outside the channel region to avoid the sacrifice in total drain current normally inherent in MMC and trigate devices.⁸⁴⁾ The developed HEMT with 3DFP, also referred to as a multi-grooved field plate (MGFP), exhibited almost collapse-free operation with essentially negligible penalty in the total drain current density. Typical values of groove length, width, depth, and spacing were 2.5, 0.3, 0.2, and 0.9 µm, respectively. Figure 16 compares NDR as a function of V_{ds_off} of the reference device (without FP) and the 3DFP HEMT at different values of on-state gate voltage (V_{gs_on}). The reference device exhibited almost overlapping NDR–V_{ds_off} curves with varying V_{gs_on}, whereas the 3DFP HEMT showed NDR–V_{ds_off} curves highly sensitive to the applied V_{gs_on}. For the 3DFP HEMT, at a given V_{ds_off}, a more positive V_{gs_on} resulted in a lower NDR, a trend typically observed from gate-FP devices as discussed above. However, this tendency of decreasing NDR, and therefore weakening current collapse with increasing V_{gs_on}, was clearly more pronounced in the 3DFP HEMT. The resulting side-wall structures confined in the FP area, which allows not only vertical, but also lateral "field-effect action" during the on-state, helped in the faster recovery of trapped electrons responsible for current collapse, thereby intensifying the FP mitigating effect. As shown in Fig. 16, the 3DFP-HEMT exhibited an NDR value of essentially equal to 1 even at V_{ds_off} of as high as 150 V, suggesting that this device may hold the key toward true "collapse-free" operation.

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