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Über dieses Buch

This book introduces readers to the emerging carbon nanotube field-effect transistor (CNTFET) technology, and examines the problem of designing efficient arithmetic circuits in CNTFET technology. Observing that CNTFETs make it possible to achieve two distinct threshold voltages merely by altering the diameter of the carbon nanotube used, the book begins by discussing the design of basic ternary logic elements. It then examines efficient CNTFET-based design of single and multiple ternary digit adders by judicious choice of unary operators in ternary logic, as well as the design of a ternary multiplier in CNTFET technology, and presents detailed simulation results in HSPICE. Lastly, the book outlines a procedure for automating the synthesis process and provides sample code in Python.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
There has been tremendous growth in the semiconductor industry in the last few decades. This has largely followed Gordon Moore’s prediction in the 1960s that number of transistors per chip would double every two years approximately. However, there have been concerns about scaling limits of silicon MOSFETs during the last twenty years [1]. As a consequence, variations of the basic theme have been suggested and two categories have emerged, one of which attempts further miniaturization while the other aims at diversification.
K. Sridharan, B. Srinivasu, Vikramkumar Pudi

Chapter 2. Basics of CNTFET and Ternary Logic

Abstract
In this chapter, we present key aspects of the CNTFET technology. As indicated earlier, carbon nanotubes have bandgaps that are dependent on the diameter of the tubes [1]. Also, the bandgap turns out to be a measure of the threshold voltage of the CNTFET.
K. Sridharan, B. Srinivasu, Vikramkumar Pudi

Chapter 3. CNTFET-Based Circuits for Basic Logic Elements

Abstract
In this chapter, we begin the transistor-based design study with basic logic elements. We start with ternary inversion and present CNTFET-based circuits. We use transistors (CNTFETs) as load analogous to [1]. However, our approach in general, does not employ decoder and encoder pairs (unlike [1]).
K. Sridharan, B. Srinivasu, Vikramkumar Pudi

Chapter 4. CNTFET-Based Design of a Single Ternary Digit Adder

Abstract
Just as we add two bits in a (binary) half-adder and three bits in a (binary) full-adder, one can consider addition of two or three ternary digits. The addition of two ternary digits is expressed by Table 4.1. The extension to three ternary digits is presented in Table 4.2.
K. Sridharan, B. Srinivasu, Vikramkumar Pudi

Chapter 5. CNTFET-Based Design of a Multi-ternary Digit Adder

Abstract
In the previous chapter, we have explored efficient design of CNTFET-based circuits for single ternary digit addition. In this chapter, we consider an extension.
K. Sridharan, B. Srinivasu, Vikramkumar Pudi

Chapter 6. CNTFET-Based Design of a Ternary Multiplier

Abstract
We have discussed the design of CNTFET-based adders in the earlier chapters. In this chapter, we present the design of a ternary multiplier. We note that the design of a single-digit multiplier itself is non-trivial in the ternary setting.
K. Sridharan, B. Srinivasu, Vikramkumar Pudi

Chapter 7. Simulation Studies

Abstract
In previous chapters, we have developed CNTFET-based designs for arithmetic operations such as addition and multiplication. In this chapter, we provide detailed simulation results for various circuits developed in the earlier chapters.
K. Sridharan, B. Srinivasu, Vikramkumar Pudi

Chapter 8. Automating the Synthesis Process

Abstract
In previous chapters, we have developed CNTFET-based designs for specific operations such as addition and multiplication. We provided various “thumb-rules” for reducing the transistor count. In this chapter, we attempt to answer the following question: Can the process of synthesis be automated ? We provide an outline of an automatic synthesis procedure and also touch upon coding in Python. A study of the synthesis problem is also pursued in [1].
K. Sridharan, B. Srinivasu, Vikramkumar Pudi

Chapter 9. The Road Ahead

Abstract
This research has studied digital design in the context of emerging nanotechnologies. In particular, we have studied the problem of designing arithmetic circuits in Carbon Nanotube Field Effect Transistor technology. We have presented a number of theoretical results on ternary logic. The results facilitate reduction of transistor count for various circuits. We now list the contributions and touch upon extensions to the work.
K. Sridharan, B. Srinivasu, Vikramkumar Pudi

Backmatter

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