Low-Power Analog Techniques, Sensors for Mobile Devices, and Energy Efficient Amplifiers

Energy harvesters are used to scavenge energy from the ambient, such as light, heat, and vibration, to power wireless sensor nodes. However, power conditioning circuits are needed to maximize conversion efficiency and convert unstable input voltages, either DC or AC, to stable DC output voltages that can be used for sensors or wireless transmitters. The available ambient energy depends on the applications, but each energy source has its own advantages and limitations. Light can be converted to DC electricity through photovoltaic (PV) principle, heat can be converted to DC through thermoelectricity, and vibration energy can be harvested through piezoelectricity or electromagnetic induction mechanism. While light is the most pervasive and has excellent energy density outdoors, its energy density is much lower indoors, and it requires large surface area that can be prohibitive for some applications. Thermoelectric harvester can generate electricity through temperature differences, but in many cases, it would require heat sink to reduce external thermal resistance to build enough temperature difference across the device. It is quiet and reliable with no moving parts. Vibration is pervasive, but vibrational harvester has narrow bandwidth, and its efficiency can drop significantly once the external vibration frequency deviates from resonant frequency for the harvesters. From power conditioning point of view, PV requires maximum power point tracking which itself will consume some currents. Output voltages from the thermoelectric harvester are usually small with limited temperature differences, so step-up would be needed. Load impedance needs to match the internal impedance for maximum power, and output AC output from vibration harvesters need to be rectified. In this chapter, we will go over the common energy harvesters and their power conditioning circuits.

IoT devices are powered by batteries that need recharging or replacement on a regular basis. With an increasing number of IoT devices per person, this will become impractical. This chapter presents an example of an energy harvesting system that allows these IoT devices to be powered by alternative energy sources like light, heat, or RF energy. Some circuits and algorithms that are specifically important for energy harvesting are discussed in more detail.

Presented are structural and circuit techniques for DCDC converters with consumption below power switch leakage and having efficiency above 80% at load currents from few μA to 100 s of mA. These techniques have been used in industrial ICs of energy harvesting systems, in the wireless sensor network power management, and in IoT electronics. Considered are process selection, transistor sizing for nA currents, biasing, voltage references, active rectifiers, comparators, oscillators, error amplifiers, and inductor current measurement, followed by selection of the DCDC operation mode and IC design examples.

This chapter targets low-power techniques for nanopower SAR ADCs with reference voltage generation. First of all, a 106nW 10b 80 kS/s SAR ADC with duty-cycled reference generation is presented, where a CMOS voltage reference, a duty-cycling block, and a LDO are integrated with the SAR ADC together. Furthermore, a low-power bidirectional comparator is utilized in the SAR ADC to reduce the power consumption. The reference-included SAR ADC achieves a FoM of 2.4fJ/conv.-step. Second, an energy-free DAC reset technique, “swap-to-reset,” is presented to deal with the large DAC reset energy in a SAR ADC, which is usually large compared with DAC conversion energy. In the prototype, the DAC energy consumption is reduced by one-third with “swap-to-reset” applied to the 2 MSBs. Finally, a low-power and area-efficient discrete-time reference driver is introduced. By calculating the energy consumption of each switching step, the DAC in a SAR ADC can be driven by a pre-charged decoupling capacitor compensated by a small auxiliary DAC. In the prototype, the SNDR/SFDR are improved by 2.7 dB/11.6 dB after enabling the 3b DAC compensation and the discrete-time reference driver only adds 10.8% and 10.1% to the power and chip area of the SAR ADC, respectively.

Duty-cycling is required to reduce the overall power consumption in IoT systems to extend the battery lifetime, which requires ultra-low-power clock generations. In this work, both the role of clocking in the whole system and the technical challenges for on-demand burst-mode operation will be discussed. In addition, an overview of state-of-the-art low-energy clock generation techniques and their performance trade-offs in terms of frequency, stability, and noise will be provided. As an example, we will show two clock generation circuits to illustrate how the challenges can be addressed.

A duty-cycled bridge-to-digital converter (BDC) for small battery operated pressure sensing systems is presented and demonstrated in two complete microsystems. By heavily duty-cycling an excitation voltage for the bridge sensor, 6000× less excitation power is consumed compared with conventional DC biasing. The excitation voltage is sampled and used to generate an ADC reference voltage to avoid line voltage fluctuation. The BDC achieves 49.2 dB SNR and 2.5 nJ conversion energy with 10.6 pJ/c.s. FOM.

This chapter presents an overview of the technology behind capacitive sensing in mobile devices and beyond. Capacitive-sensing systems handle signals from the pF range down to aF. Examples to illustrate this include “single-pixel” buttons, sliders, touch screens, and “kilo-pixel” fingerprint readers.

Challenges and solutions for sensors, architectures, algorithms, and circuit technology are discussed.

Despite MEMS microphone market getting more mature, the demand is still increasing due to the integration of several units in the same mobile device. Moreover, product specifications are pushing toward contradicting directions—increase of Signal-to-Noise Ratio (SNR) and Acoustic Overload Point (AOP)—with a continuous miniaturization of the package and power savings. To achieve those targets, the development of both the sensor and the readout circuitry must proceed in close interaction to allow trade-offs and define irremovable constraints. The use of behavioral models for the sensor as well as the package allows tailoring the design of the readout electronics to the specific requirements of the acoustical system, leading to the optimum performance in terms of noise and power consumption. After introducing the most commonly used techniques to map the electroacoustical properties of transducer and package, a design example of a state-of-the-art digital microphone system with 140 dB SPL full scale and achieving an SNR of 67 dB at the reference level of 94 dB SPL is presented.

This chapter presents a high-performance dual-axis (pitch and roll) MEMS vibratory gyroscope readout ASIC which converts angular rate information to digital output. Two signal-processing chains surrounding the MEMS sensor are implemented, namely the drive channel and the sense channel. The drive channel drives the sensor to resonate at its resonant frequency, which produces a velocity of the sensor disc to generate the Coriolis force during angular rotation. The sense channel employs a low noise transimpedance amplifier (TIA) followed by a demodulator (DM), which down converts the angular rate input signal from the resonant frequency to baseband. Two switched-capacitor (SC) 2–1 MASH delta-sigma ADCs convert the input angular rate from the pitch and roll arises to digital output. The reference of the ADC is also demodulated from the sensor output to cancel out supply voltage dependence. The whole ASIC, including the high-voltage MEMS sensor driver, digital filter, on-chip regulator, and temperature sensor, is fabricated in a 0.18 μm CMOS technology with an area of 7.3 mm². The design achieves a noise floor of 0.0032°/s/√Hz and 0.0061°/s/√Hz in full-scale input ranges of 500°/s and 2000°/s, respectively, over a 480 Hz signal bandwidth. The bias instability is measured as 2.5°/h at input range of 500°/s. The whole ASIC consumes 7 mA from a 3 V supply.

The FM gyroscope measures rate directly as a frequency variation and employs rate chopping to reject drift. The scale factor is set by a reference clock. Symmetric and asymmetric readout modes enable trading off long- versus short-term errors without changing the transducer or circuits. Chopped at 10 Hz, the prototype achieves better than 40 ppm scale factor accuracy, 1.5 deg/h^1.5 rate random walk in symmetric mode, and 1 mdps/rt-Hz ARW in asymmetric mode.

This chapter presents two cost-effective sensors that measure ambient carbon dioxide (CO₂) concentration, intended for application in smart ventilation systems in buildings or in mobile devices. Both sensors employ a suspended hot-wire transducer to detect the CO₂-dependent thermal conductivity (TC) of the ambient air. The resistive transducer is realized in the VIA layer of a standard CMOS process using a single etch step. The first sensor determines the transducer’s CO₂-dependent thermal resistance to the surrounding air by measuring its steady-state temperature rise and power dissipation. A ratiometric measurement is realized by employing an identical but capped transducer as a reference. An incremental delta-sigma ADC digitizes the temperature and power ratios of the transducers, from which the ratio of the thermal resistances is calculated. The second sensor is based on a transient measurement of the CO₂-dependent thermal time constant of the transducer. The readout circuit periodically heats up the transducer and uses a phase-domain delta-sigma modulator to digitize the CO₂-dependent phase shift of the resulting temperature transients. Compared to the ratiometric steady-state measurement, this approach significantly reduces the measurement time and improves the energy efficiency, resulting in a state-of-the-art CO₂ resolution of 94 ppm at an energy consumption of 12 mJ per measurement.

Optical sensors, based on the time correlated single photon counting (TCSPC) technique, are found in a range of applications from medical to consumer. This chapter provides an overview of the challenges in TCSPC sensor design for mobile applications. We describe the design of a proof-of-concept TCSPC optical sensor with 10 GS/s conversion rate folded flash time to digital converter (TDC) and on-chip histogram generation, designed to minimize time-domain distortion and have high power efficiency. The proof of concept IC is fabricated in STMicroelectronics 130 nm SPAD foundry process. The system consumes 178.1 pJ per photon at 899 M photon/s, and the TDC achieves state of the art 0.48 pJ/S energy efficiency.

A comprehensive method for power estimation of residue amplifiers is presented. Using this method a definition of power efficiency is given, which subsequently is used to analyze recently published, highly efficient residue amplifiers. Design parameters are identified which have a key influence on the power efficiency, and design choices based on power efficiency are discussed. It is shown that the most power-efficient residue amplifier topologies share the same core circuit and differ primarily in how this core circuit is driven from the input. Finally, an overview is given of these topologies, ranked on power efficiency.

The continuous feature size scaling in CMOS has enabled the system to decrease power consumption. However, the operational amplifiers, which have been the backbone of analog circuits, face significant challenges in the scaled CMOS technology. Dynamic amplifiers based on CMOS inverters attract again and have become essential to maximize energy efficiency in all analog building blocks. This chapter discusses the design of energy-efficient inverter-based amplifiers that include operating principle and biasing techniques. It also covers recent advances to prevent performance degradation of inverter-based circuits and design examples of the state-of-the-art inverter-based amplifiers.

Class-D amplifiers typically require more external components than class-AB amplifiers to achieve high efficiency and keep electromagnetic interference (EMI) under control. In this chapter, an overview is given of innovative class-D architectures and how they balance efficiency, EMI, and application cost.

This chapter presents a digital Class D amplifier targeted at deep sub-micron process nodes, where digital processing is cheap and analog is expensive in terms of area and power. The architecture uses open-loop and closed-loop configurations and combines the concepts of both to provide high performance over the full signal range. At low-signal levels, low noise and power is achieved with open-loop digital operation. At larger signal levels, a closed-loop digital Class D mode is used to deliver low THD and high PSRR with minimal analog circuitry.

Audio interfaces are among the most popular interfaces between man and machines. Such interfaces are based on microphones, whose efficiency expressed in terms of performance/power consumption is becoming one of the crucial parameters for the success on the market. In this chapter, the main specifications of typical microphone interfaces are illustrated to exhibit the advances in their development toward the maximization of their efficiency.

Wireless communication is shifting to the millimeter wave frequencies, driven by large bandwidths and accelerated by the discussions on 5G. Phased arrays with multiple front-ends and antennas are inevitable to overcome signal losses, emphasizing the need for low-power solutions. An overview of several analog and digitally modulated transmitter architectures and implementations at millimeter waves is presented. Digital implementations have a potential to save the transmitter power consumption as they allow the power amplifier to operate in saturation. The reduced combination efficiency and complex calibration in digital I-Q architectures risk its power saving advantage. On the other hand, front-ends in digital polar architectures can be highly efficient. Despite having a higher bandwidth baseband and more complex digital processing, high-efficiency front-ends in digital polar architectures are closer to show a power consumption advantage in phased arrays, where the front-end contribution dominates.