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Über dieses Buch

Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base.

LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination.

The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r

egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

This is the age of handheld devices and it is a demand of the standard design verification flow that every chip design today needs to be low-power (LP).
Progyna Khondkar

Chapter 2. Background

It is now time for the chip design and verification community to take a closer look at the semiconductor physics fundamentals, since Moore’s law still holds true after a half century. Gordon Moore forecast in 1965 that transistor integration in chips will double every 2 years. One of the prime reasons the law still holds true, defying chip area congestions, is because of the drastic advancement of the integrated circuits fabrication and process technology. TSMC foundry is in fabrication process of 10 and 7 nm technology from early 2017.
Progyna Khondkar

Chapter 3. Modeling UPF

As explained in the previous Chapter 2, the modeling of UPF comprises the precise mapping of power specifications of a design, hence the development of such a specification usually starts with the prerequisite design targets, whether it is SoC, ASIC, MCU, or processor core. It is also required to determine the best power management and reduction techniques applicable for the design. The obvious next objective is to capture every detail of the adopted techniques in parameterized attributes for both HDL references and user-defined variables in order to construct UPF files.
Progyna Khondkar

Chapter 4. Power Aware Standardization of Library

Multivoltage (MV) based power aware (PA) design verification and implementation methodologies require special power management attributes in libraries for standard, MV and Macro cells for two distinctive reasons. The first aspect is to provide power and ground (also bias) supply or PG-pin information, which is mandatory for PA verification. The second reason is to provide a distinctive attribute between a special power management MV cell and a regular standard cell. The special MV cells include isolation (ISO), level-shifters (LS), enable level-shifter (ELS), always-on buffers (AOB), feed through buffers or repeaters (RPT), diode clamps, retention flops (RFF), power switches (PSW), multi- and single- rail Macros. This Chapter describes the standard requirements of Power Aware or PG-pin libraries and provides modeling examples of the MV cells from UPF based PA verification perspective.
Progyna Khondkar

Chapter 5. UPF Based Power Aware Dynamic Simulation

UPF based power aware (PA) verification adopts several power dissipation reduction techniques based on the target design implementation and UPF power specification or intent, as discussed in Chap. 2. These techniques introduce numerous and complex verification issues and challenges in the functional and structural aspects of the design. Such artifacts are completely nonexistent in a non-PA verification environment. For example, the power aware requirements may affect the design functionality in terms of power On-Off sequences, different modes of power operation, state or data preservation operations, data propagation, logic resolution, power state transitions, power state transition coverage, power state cross coverage, and more.
Progyna Khondkar

Chapter 6. Power Aware Dynamic Simulation Coverage

Coverage provides meaningful insight into design verification completeness. The coverage metric in dynamic simulation is a system or standard of measurement used to describe the degree to which the design is exercised with certain design parameters for a particular test-suite or test-plan execution. Even the test-plan is subject to measurement using a weighted metric and recapitulated to contribute to the total resultant coverage metric.
Progyna Khondkar

Chapter 7. UPF Based Power Aware Static Verification

PA-Static verification, more popularly known as PA-Static checks, are performed on designs that adopt certain power dissipation reduction techniques through the power intent or UPF. The term static originates from verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requirements, statically on the structure of the design. More precisely, the rule sets are applied on the physical structure, architecture, and microarchitecture of the design, in conjunction with the UPF specification but without the requirements of any external stimulus or testbenches.
Progyna Khondkar

Backmatter

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