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2015 | OriginalPaper | Buchkapitel

Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS

verfasst von : João Goes, Nuno Pereira

Erschienen in: High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

Verlag: Springer International Publishing

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Abstract

This chapter reviews recent advances in low-power design techniques for high-speed and high-effective resolution pipeline Analog-to-Digital Converters (ADCs). The advantages of replacing, in a pipeline ADC architecture, the traditional local low-resolution parallel (flash) quantizers by low-resolution successive-approximation register (SAR) ADCs are shown through a set of selected works. Some of the most promising energy-efficient residue amplification techniques are reviewed, spanning from open-loop and closed-loop amplifierless approaches to innovative and highly-scalable amplifier-based topologies.

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Nächstes Kapitel Digitally Assisted Analog to Digital Converters
Literatur
1.
S. Devarajan, et. al., “A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC”, IEEE J. Solid State Circuits, vol. 44, 3305–3313, Dec. 2009.
2.
S. Ray, B.-S. Song, “A 13-bit Linear, 20-MS/s Pipeline ADC With Self-Configured Capacitor Matching”, IEEE J. Solid State Circuits, vol. 42, 463–474, Mar. 2007.
3.
R. Aparicio, A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors”, IEEE J. Solid State Circuits, vol. 37, 384–394, Mar. 2002.
4.
J. Goes et. al., “Purely-Digital versus Mixed-Signal Self-Calibration Techniques in High-Resolution Pipeline ADCs”, Proc. NORCHIP’2010, pp. 1–8, Finland, Nov. 2010.
5.
M. Saberi, R. Lotfi, k. Mafinezhad, W. A. Serdijn, “Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs”, IEEE Transactions on Circuits and Systems – I, vo. 58, nº. 8, pp. 1736–1748, Aug. 2011.
6.
Y.-D. Jeon et al., “A 9.15mW 0.22 mm2 10b 204MS/s pipelined SAR ADC in 65 nm CMOS”, in 2010 IEEE Proc. CICC, pp. 1–4, 2010.
7.
C. C. Lee and M. P. Flynn, “A SAR-Assisted Two-Stage Pipeline ADC”, IEEE Journal of Solid-State Circuits, vol. 46, n. 4, pp. 859–869, April 2011.
8.
Y. Zhu et al., “A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation”, IEEE Journal of Solid-State Circuits, vol. 47, n. 11, pp. 2614–2626, Nov. 2012.
9.
B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS”, IEEE Journal of Solid-State Circuits, vol. 47, n. 12, pp. 2880–2887, Dec. 2012.
10.
I. Ahmed, J. Mulder, D. A Johns, “A Low-Power Capacitive Charge Pump Based Pipelined ADC”, IEEE Journal of Solid-State Circuits, vol. 45, n. 5, pp. 1016–1027, May 2010.
11.
J. Hu, N. Dolev, B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification”, IEEE Journal of Solid-State Circuits, vol. 44, n. 4, pp. 1057–1066, April 2009.
12.
J. Oliveira, J. Goes, et. al., “An 8-bit 120 MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification”, IEEE Transactions on Circuits and Systems – II, pp. 105–109, Feb. 2010.
13.
S. Ranganathan and Y. Tsividis, “Discrete-time parametric amplification based on a three-terminal MOS varactor: Analysis and experimental results”, IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2087–2093, Dec. 2003.
14.
J. K. Fiorenza et. al., “Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies”, IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658–2668, Dec. 2006.
15.
L. Books and H.-S. Lee, “A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC”, IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2677–2687, Dec. 2007.
16.
J. Chu and H.-S. Lee, “A Zero-Crossing Based 12b 100MS/s Pipelined ADC with Decision Boundary Gap Estimation Calibration”, IEEE Proc. VLSI Circuits, pp. 237–238, 2010.
17.
J. Kuppambatti and P. R. Kinget, “A Low-Power Zero-Crossing Pipeline-SAR ADC with On-Chip Dynamically Loaded Pre-Charged Reference”, IEEE Proc. ESSCIRC’13, pp. 113–116, 2013.
18.
B. McMillan, “Multiple-Feedback Systems”, US patent 2,748,201, May 1956.
19.
S.-W. Sin, S.-P. U, R. P. Martins, “Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps”, IEEE Transactions on Circuits and Systems – I, pp. 2188–2201, Sep. 2008.
20.
Y. Miyahara, et. al., “Adaptive Cancellation of Gain Nonlinearity Errors in Pipelined ADCs”, IEEE Proc. ISSCC’13, pp. 282–283, 2013.
21.
S.-H. W. Chiang, H. Sun, Behzad Razavi, “A 10-Bit 800-MHz 19-mW CMOS ADC”, IEEE Proc. VLSI Circuits, pp. C100–C101, 2013.
22.
B. Hershberg, et. al., “Ring Amplifiers for Switched-Capacitor Circuits”, IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2928–2942, Dec. 2012.
23.
B. Hershberg and Un-Ku Moon, “A 75.9 dB-SNDR 2.96mW 29fJ/conv-step Ringamp-Only Pipelined ADC”, IEEE Proc. VLSI Circuits, pp. C94–C95, 2013.
24.
M. Figueiredo, G. Evans, J. Goes, “Reference-Free High-Speed CMOS Pipeline Analog-to-Digital Converters”, Springer, ISBN 978-1-4614-3466-5, 2013.
25.
M. Figueiredo, G. Evan, J. Goes, “A Reference-Free 7-bit 500 MS/s Pipeline ADC Using Current-Mode Reference Shifting and Built-in Threshold Quantizers”, Analog Integrated Circuits and Signal Processing Journal (AICSP, Springer), vol. 75. no. 1, pp. 53–65, 2013.
26.
P. Quinn and M. Pribytko, “Capacitor Matching Insensitive 12-bit 3.3 MS/s Algorithmic ADC in 0.25 μm CMOS”, IEEE Proc. CICC’03, pp. 425–426, 2003.
27.
Y.-C. Huang and T.-C. Lee, “A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique”, IEEE Transactions on Circuits and Systems – I, vol. 58, pp. 1157–1166, June 2011.
28.
T. Oh, H. Venkatram and U.-K. Moon, “A 70MS/s 69.3 dB SNDR 38.2fJ/conversion-step Time-Based Pipelined ADC”, IEEE Proc. VLSI Circuits, pp. C96–C97, 2013.
Metadaten
Titel
Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS
verfasst von
João Goes
Nuno Pereira
Copyright-Jahr
2015
Buch
High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

Print ISBN: 978-3-319-07937-0

Electronic ISBN: 978-3-319-07938-7

Copyright-Jahr: 2015

DOI
https://doi.org/10.1007/978-3-319-07938-7_1

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