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Erschienen in:

2025 | OriginalPaper | Buchkapitel

Low Power Low Area Approximate Multipliers with New Compressors

verfasst von : N. Bhuvan Praneeth, N. Krishna Priya, K. Sandhya, Sarada Musala

Erschienen in: Proceedings of Third International Conference on Computational Electronics for Wireless Communications

Verlag: Springer Nature Singapore

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Abstract

In several applications where exact computation is not essential, approximate computing is a developing paradigm for sacrificing computing accuracy to save energy and simplify design complexity. This brief presents a low-power, low-area approximate multiplier with a new compressor design. The proposed multiplier handles the component that is least crucial as a fixed compensating term. The second half features a carefully considered hardware–accuracy trade-off that is tremendously powerful. Efficiency is provided. The proposed multiplier is simulated using CADENCE with 18 nm FinFET technology. Compared to the current approximation designs, the proposed design 1 significantly reduces transistor count by 2.05% and power on average by 1.9%, and the proposed design 2 significantly reduces power on average by 3.9% and transistor count by 9.51%. As a result, these designs can be an efficient replacement for exact multipliers in real-world applications that are error-tolerant.

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Metadaten
Titel
Low Power Low Area Approximate Multipliers with New Compressors
verfasst von
N. Bhuvan Praneeth
N. Krishna Priya
K. Sandhya
Sarada Musala
Copyright-Jahr
2025
Verlag
Springer Nature Singapore
DOI
https://doi.org/10.1007/978-981-97-1943-3_1