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2022 | OriginalPaper | Buchkapitel

Low-Power SRAM Memory Architecture for IoT Systems

verfasst von : Reeya Agrawal

Erschienen in: Recent Advances in Manufacturing, Automation, Design and Energy Technologies

Verlag: Springer Singapore

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Abstract

A quantitative and yield analysis of single-bit cache memory architecture with different types of sense amplifiers such as voltage-mode differential sense amplifier (VMDSA), has been implemented and compared on different values of resistance (R). Results depicted that the single-bit cache memory architecture having voltage-mode differential sense amplifier consumes the lowest power (11.16 µW). This SRAM is specifically suitable for Internet-of-Things (IoT) applications with slow access rates and low power consumption.

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Vorheriges Kapitel Analysis of Cache Memory Architecture Design Using Low-Power Reduction Techniques for Microprocessors

Nächstes Kapitel Design and Structural Analysis of Nano-satellite

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Titel: Low-Power SRAM Memory Architecture for IoT Systems
verfasst von: Reeya Agrawal
Verlag: Springer Singapore
Buch: Recent Advances in Manufacturing, Automation, Design and Energy Technologies
Print ISBN: 978-981-16-4221-0

Electronic ISBN: 978-981-16-4222-7

Copyright-Jahr: 2022
DOI: https://doi.org/10.1007/978-981-16-4222-7_57

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