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Erschienen in:
2000 | OriginalPaper | Buchkapitel
Machine Assisted Verification
verfasst von : Hans Eveking
Erschienen in: Architecture Design and Validation Methods
Verlag: Springer Berlin Heidelberg
Enthalten in: Professional Book Archive
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An introduction to a number of fully mechanized methods of formal hardware verification is given. Decision-diagram based procedures for the verification of combinational circuits at the gate- and word-level are surveyed. Fixed-point calculation techniques for equivalence and property verification of sequential machines are studied. The verification of processor architectures at the instruction-set and algorithmic register-transfer level is discussed. A method of formally correct synthesis of pipelined architectures is presented.