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This book provides readers with an up-to-date account of the use of machine learning frameworks, methodologies, algorithms and techniques in the context of computer-aided design (CAD) for very-large-scale integrated circuits (VLSI). Coverage includes the various machine learning methods used in lithography, physical design, yield prediction, post-silicon performance analysis, reliability and failure analysis, power and thermal analysis, analog design, logic synthesis, verification, and neuromorphic design.

Provides up-to-date information on machine learning in VLSI CAD for device modeling, layout verifications, yield prediction, post-silicon validation, and reliability;

Discusses the use of machine learning techniques in the context of analog and digital synthesis;

Demonstrates how to formulate VLSI CAD objectives as machine learning problems and provides a comprehensive treatment of their efficient solutions;

Discusses the tradeoff between the cost of collecting data and prediction accuracy and provides a methodology for using prior data to reduce cost of data collection in the design, testing and validation of both analog and digital VLSI designs.

From the Foreword

As the semiconductor industry embraces the rising swell of cognitive systems and edge intelligence, this book could serve as a harbinger and example of the osmosis that will exist between our cognitive structures and methods, on the one hand, and the hardware architectures and technologies that will support them, on the other….As we transition from the computing era to the cognitive one, it behooves us to remember the success story of VLSI CAD and to earnestly seek the help of the invisible hand so that our future cognitive systems are used to design more powerful cognitive systems. This book is very much aligned with this on-going transition from computing to cognition, and it is with deep pleasure that I recommend it to all those who are actively engaged in this exciting transformation.

Dr. Ruchir Puri, IBM Fellow, IBM Watson CTO & Chief Architect, IBM T. J. Watson Research Center



Chapter 1. A Preliminary Taxonomy for Machine Learning in VLSI CAD

Machine learning is transforming many industries and areas of work, and the design of very large-scale integrated (VLSI) circuits and systems is no exception. The purpose of this book is to bring to the interested reader a cross-section of the connections between existing and emerging machine learning methods and VLSI computer aided design (CAD). In this brief introduction, we begin with a high-level taxonomy of machine learning methods. We then turn to the design abstraction hierarchy in VLSI CAD, and note the needs and challenges in design where machine learning methods can be applied to extend the capabilities of existing VLSI CAD tools and methodologies. Finally, we outline the organization of this book, highlighting the range of machine learning methods that each of the chapters contributed to this book build on.
Duane S. Boning, Ibrahim (Abe) M. Elfadel, Xin Li

Part I


Chapter 2. Machine Learning for Compact Lithographic Process Models

This chapter described the motivations and requirements for compact patterning models, and the role of machine learning in constructing them. We start by defining patterning process models and their role in the IC fabrication process. We then describe the requirements of these models, in particular with regard to turn-around time in production high-volume manufacturing, which usually necessitates the use of compact patterning process models rather than rigorous models. We describe the stages into which the pattern process can be subdivided, and the challenges of modeling each stage. We then move to the discussion of supervised learning as it has been applied to the problem of training compact patterning process models. In the final section, we review some of recent results in applying deep learning to this domain.
J. P. Shiely

Chapter 3. Machine Learning for Mask Synthesis

Recent mask synthesis takes longer runtime due to the demand on higher accuracy. It is common that optical proximity correction (OPC) takes a few days. Machine learning has recently been applied to mask synthesis process with some success. This chapter addresses two popular mask synthesis tasks, OPC and etch proximity correction (EPC), and presents how machine learning is applied for their efficient implementation. Discussion on learning parameters, preparation of learning data set, and techniques to avoid over-fitting are also provided.
Seongbo Shim, Suhyeong Choi, Youngsoo Shin

Chapter 4. Machine Learning in Physical Verification, Mask Synthesis, and Physical Design

Yield, turn-around time, and chip quality are always of significant concerns for VLSI designs. The performance and efficiency of key design steps such as physical design, mask synthesis, and physical verification are critical to guarantee fast design closure and manufacturability. Recent advances in machine learning provide various new opportunities and approaches to tackle these challenges. This chapter will discuss several applications of machine learning in the backend design flow and demonstrate its impacts to existing design automation methodology.
Yibo Lin, David Z. Pan

Part II


Chapter 5. Gaussian Process-Based Wafer-Level Correlation Modeling and Its Applications

Semiconductor fabrication is one of the most intricate, multistep, human-made processes, taking place every day, producing trillions of transistors every second. The complexity of this manufacturing process naturally introduces variations with every stage affecting the produced devices differently. These variations can be observed at different granularity levels, within every die, across die at wafer level, across lots, and holistically for the entire production. Understanding and addressing such variations is the primary objective for many engineering roles, ranging from designers, to process engineers, and to test engineers. In this chapter, we focus on understanding and modeling wafer-level spatial and spatiotemporal variations through the use of Gaussian processes and we present various real-life applications of such modeling in test cost reduction, quality improvement, and yield learning.
Constantinos Xanthopoulos, Ke Huang, Ali Ahmadi, Nathan Kupp, John Carulli, Amit Nahar, Bob Orr, Michael Pass, Yiorgos Makris

Chapter 6. Machine Learning Approaches for IC Manufacturing Yield Enhancement

Modern semiconductor manufacturing is highly automated and generates a large amount of data with every wafer and process step. There is an increasing interest in machine learning and data mining techniques to improve yield to take advantage of this increasing volume of data. In this chapter, we introduce machine learning yield models for integrated circuit (IC) manufacturing yield enhancement. Challenges in this area include class imbalance due to high manufacturing yield, and concept drift due to the time-varying environment. We present batch and online learning methods to tackle the imbalanced classification problem, and incremental machine learning frameworks to overcome concept drift. We consider the packaging and testing process in chip stack flash memory manufacturing as an application. By testing our methods on real data from industry, we show the possibility of packaged memory yield improvement with machine learning-based classifiers detecting bad dies before packaging. Experimental results show significant yield improvement potential. In a time-invariant environment, for stacks of eight dies, we can achieve an approximately 9% yield improvement. In a longer period of time with realistic concept drift, a naive approach using a fixed false alarm rate-based decision boundary is shown to fail to improve yield. In contrast, with optimal thresholds, our incremental learning approach achieves approximately 1.4% yield improvement in the eight-die stack case and 3.4% in the 16-die stack case.
Hongge Chen, Duane S. Boning

Chapter 7. Efficient Process Variation Characterization by Virtual Probe

In this chapter, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize, and monitor spatially correlated inter-die and/or intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs in compressed sensing to accurately predict spatial variations from an exceptionally small set of measurement data, thereby reducing the cost of silicon characterization. By exploring the underlying sparse pattern in spatial frequency domain, VP achieves substantially lower sampling frequency than the well-known Nyquist rate. In addition, VP is formulated as a linear programming problem and, therefore, can be solved both robustly and efficiently. Our industrial measurement data demonstrate the superior accuracy of VP over several traditional methods including two-dimensional interpolation, Kriging prediction, and k-LSE estimation.
Jun Tao, Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton, Xuan Zeng

Chapter 8. Machine Learning for VLSI Chip Testing and Semiconductor Manufacturing Process Monitoring and Improvement

Machine learning and big data analytics are the latest spotlights with all the glare of fame ranging from media coverage to booming start-up companies to eye-catching merges and acquisitions. On the contrary, the $336 billion industry of semiconductor was seen as an “old-fashioned” business, with fading interests from the best and brightest among young graduates and engineers. This chapter argues that this does not have to be that way because many research problems and solutions as studied in the semiconductor industry are in fact closely related to these machine learning and big data problems. To illustrate this point, we discuss a number of practical but challenging problems arising from semiconductor manufacturing process in this chapter. We first show how machine learning techniques, especially those regression-related problems, often under the “disguise” of optimization problems, have been used frequently (often with nontrivial modeling skills and mathematical sophistications) to solve the semiconductor problems. We discuss such examples as process variation modeling and VLSI chip testing. For some other types of semiconductor problems, such as manufacturing process monitoring and improvement, we show that some existing machine learning algorithms are not necessarily well positioned to solve them, and novel machine learning techniques involving temporal, structural, and hierarchical properties need to be further developed. In either scenario, we convey the message that machine learning and existing semiconductor industry researches are closely related, and researchers often contribute to and benefit from each other.
Jinjun Xiong, Yada Zhu, Jingrui He

Chapter 9. Machine Learning-Based Aging Analysis

Bias temperature instability (BTI)-induced transistor aging, one of the major reliability threats in nanoscale VLSI, degrades path delay over time and may lead to timing failures. Runtime solutions based on online monitoring and adaptation are required for resilience in nanoscale integrated circuits, as design-time solutions and guard bands are no longer sufficient. Chip health monitoring is, therefore, necessary to track delay changes on a per-chip basis over the chip lifetime operation. However, direct monitoring based on actual measurement of path delays can only track a coarse-grained aging trend in a reactive manner, not suitable for proactive fine-grain adaptations. We propose a low-cost and fine-grained workload-induced stress monitoring approach, based on machine learning techniques, to accurately predict aging-induced delay. We integrate space and time sampling of selective flip-flops into the runtime monitoring infrastructure in order to reduce the cost of monitoring the workload. The prediction model is trained offline using support-vector regression and implemented in software. This approach can leverage proactive adaptation techniques to mitigate further aging of the circuit by monitoring aging trends. Simulation results for realistic open-source benchmark circuits highlight the accuracy of the proposed approach.
Arunkumar Vijayan, Krishnendu Chakrabarty, Mehdi B. Tahoori

Part III


Chapter 10. Extreme Statistics in Memories

Memory design specifications typically include yield requirements, apart from performance and power requirements. These yield requirements are usually specified for the entire memory array at some supply voltage and temperature conditions. For example, the designer may be comfortable with an array failure probability of one in a thousand at 100C and 1 V supply, i.e., F f,array ≤ 10−3. However, how does this translate to a yield requirement for the memory cell? How do we even estimate the statistical distribution of memory cell performance metrics in this extreme rare event regime? We will answer these questions and in the process see the application of certain machine learning techniques and extreme value theory in memory design.
Amith Singhee

Chapter 11. Fast Statistical Analysis Using Machine Learning

In this chapter, we describe a fast statistical yield analysis methodology for memory design. At the heart of its engine is a mixture importance sampling-based methodology which comprises a uniform sampling stage and an importance sampling stage. Logistic regression-based machine learning techniques are employed for modeling the circuit response and speeding up the importance sample points simulations. To avoid overfitting, we rely on a cross-validation-based regularization framework for ordered feature selection. The methodology is comprehensive and computationally efficient. We demonstrate the methodology on an industrial state-of-the-art 14 nm FinFET SRAM design with write-assist circuitry. The results corroborate well with hardware and with the fully circuit-simulation-based approach.
Rouwaida Kanj, Rajiv V. Joshi, Lama Shaer, Ali Chehab, Maria Malik

Chapter 12. Fast Statistical Analysis of Rare Circuit Failure Events

Accurately estimating the rare failure rates for nanoscale memory circuits is a challenging task, especially when the variation space is high-dimensional. In this chapter, we summarize two novel techniques to address this technical challenge. First, we describe a subset simulation (SUS) technique to estimate the rare failure rates for continuous performance metrics. The key idea of SUS is to express the rare failure probability of a given circuit as the product of several large conditional probabilities by introducing a number of intermediate failure events. These conditional probabilities can be efficiently estimated with a set of Markov chain Monte Carlo samples generated by a modified Metropolis algorithm. Second, to efficiently estimate the rare failure rates for discrete performance metrics, scaled-sigma sampling (SSS) can be used. SSS aims to generate random samples from a distorted probability distribution for which the standard deviation (i.e., sigma) is scaled up. Next, the failure rate is accurately estimated from these scaled random samples by using an analytical model derived from the theorem of “soft maximum”. Our experimental results of several nanoscale circuit examples demonstrate that SUS and SSS achieve significantly improved accuracy over other traditional techniques when the dimensionality of the variation space is more than a few hundred.
Jun Tao, Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo, Ben Gu, Xuan Zeng

Chapter 13. Learning from Limited Data in VLSI CAD

Applying machine learning to analyze data from design and test flows has received growing interests in recent years. In some applications, data can be limited and the core of analytics becomes a feature search problem. In this context, the chapter explains the challenges for adopting a traditional machine learning problem formulation view. An adjusted machine learning view is suggested where learning from limited data is treated as an iterative feature search process. The theoretical and practical considerations for implementing such a search process are discussed.
Li-C. Wang

Part IV


Chapter 14. Large-Scale Circuit Performance Modeling by Bayesian Model Fusion

In this chapter, we describe a novel statistical framework, referred to as Bayesian Model Fusion (BMF), that allows us to minimize the simulation and/or measurement cost for both pre-silicon validation and post-silicon tuning of analog and mixed-signal (AMS) circuits with consideration of large-scale process variations. The BMF technique is motivated by the fact that today’s AMS design cycle typically spans multiple stages (e.g., schematic design, layout design, first tape-out, second tape-out, etc.). Hence, we can reuse the simulation and/or measurement data collected at an early stage to facilitate efficient validation and tuning of AMS circuits with a minimal amount of data at the late stage. The efficacy of BMF is demonstrated by using several industrial circuit examples.
Jun Tao, Fa Wang, Paolo Cachecho, Wangyang Zhang, Shupeng Sun, Xin Li, Rouwaida Kanj, Chenjie Gu, Xuan Zeng

Chapter 15. Sparse Relevance Kernel Machine-Based Performance Dependency Analysis of Analog and Mixed-Signal Circuits

Design optimization, verification, and failure diagnosis of analog and mixed-signal (AMS) circuits requires accurate models that can reliably capture complex dependencies of circuit performances on essential circuit and test parameters, such as design parameters, process variations, and test signatures. We present a novel Bayesian learning technique, namely sparse relevance kernel machine (SRKM), for characterizing analog circuits with sparse statistical regression models. SRKM produces more reliable classification models learned from simulation data with a limited number of samples but a large number of parameters, and also computes a probabilistically inferred weighting factor quantifying the criticality of each parameter as part of the overall learning framework, hence offering a powerful enabler for variability modeling, failure diagnosis, and test development. Compared to other popular learning-based techniques, the proposed SRKM produces more accurate models, requires less amount of training data, and extracts more reliable parametric ranking. The effectiveness of SRKM is demonstrated in examples including statistical variability modeling of a low-dropout regulator (LDO), built-in self-test (BIST) development of a charge-pump phase-locked loop (PLL), and applications of building statistical variability models for a commercial automotive interface design.
Honghuang Lin, Asad Khan, Peng Li

Chapter 16. SiLVR: Projection Pursuit for Response Surface Modeling

Circuit performance metrics depend on several design and process parameters of the components of the circuit. This relationship can often be quite nonlinear and in a high-dimensional space resulting from high parameter counts. We look at a response surface modeling approach that models this relationship effectively by extracting the dominant latent variables in the input space that primarily influence the performance metric. The approach is reminiscent of project pursuit, but applies that technique via a carefully crafted neural network architecture. The neural network in this case is grown dynamically in stages, where each stage extracts the next dominant latent variable and models the relationship between the performance metrics and that latent variable.
Amith Singhee

Chapter 17. Machine Learning-Based System Optimization and Uncertainty Quantification for Integrated Systems

Increasing complexity and higher integration of electronics leads to new challenges in system optimization. This is because modern systems contain structures with multi-scale geometries whose responses are determined by multi-physics simulations and often times contain components that are electromagnetically coupled. In practice, the use of optimization algorithms in the design cycle of such systems is limited to fine-tuning an already good design, which requires substantial human intervention and CPU time to arrive at an optimum solution. This is mainly due to lack of methods capable of handling high dimensionality at the same time converging to the global optimum regardless of the initial point selection. We therefore present a new, EDA oriented method, utilizing machine learning techniques to perform black-box optimization that starts with zero training data and ensures convergence to global optimum in the minimum amount of CPU time. In order to consider uncertainties in fabrication that are likely to cause deviations in the final design from the optimal design parameters, we present a ML-based uncertainty quantification (UQ) methodology. Although the combination of optimization and UQ algorithms presented in this chapter are fully automated and generic, we demonstrate these methods on an emerging application in system integration and power delivery, namely integrated voltage regulators (IVR). The IVR considered here is based on system in package (SiP) technology.
Hakki M. Torun, Mourad Larbi, Madhavan Swaminathan

Part V


Chapter 18. SynTunSys: A Synthesis Parameter Autotuning System for Optimizing High-Performance Processors

Advanced logic and physical synthesis tools provide numerous options and parameters that can drastically impact design quality; however, the large number of options leads to a complex design space difficult for human designers to navigate. By employing intelligent search strategies and parallel computing we can tackle this parameter tuning problem, thus automating one of the key design tasks conventionally performed by a human designer. To fully utilize the optimization potential of these tools, we propose SynTunSys, a system that adds a new level of abstraction between designers and design tools for managing the design space exploration process. SynTunSys takes control of the synthesis parameter tuning process, i.e., job submission, results analysis, and next-step decision making, automating one of the more difficult decision processes faced by designers. This system has been employed for optimizing multiple IBM high-performance server chips and presents numerous opportunities for future intelligent automation research.
Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Jihye Kwon, Luca P. Carloni

Chapter 19. Multicore Power and Thermal Proxies Using Least-Angle Regression

The use of performance counters (PCs) to develop per-core power and thermal proxies for multicore processors is now well established. These proxies are typically obtained using traditional linear regression techniques. These techniques have the disadvantage of requiring the full PC set regardless of the workload run by the multicore processor. Typically a computationally expensive principal component analysis is conducted to find the PCs most correlated with each workload. In this chapter, we use the more recent algorithm of least-angle regression to efficiently develop power and thermal proxies that include only PCs most relevant to the workload. Such PCs are considered workload signatures in the PC space and used to categorize the workload and to trigger specific power and thermal management action. Also, the workload signatures at both the core and the thread level are used to decide thread migration policies to maximize per-core utilization and reduce the number of active cores. Our new power and thermal proxies are trained and tested on workloads from the PARSEC and SPEC CPU 2006 benchmarks with an average error of less than 3%. Power, thermal, and performance-aware autoscaling policies are presented, and extensive numerical experiments are used to illustrate the advantages of our algorithm for real-time multicore power and performance management.
Rupesh Raj Karn, Ibrahim (Abe) M. Elfadel

Chapter 20. A Comparative Study of Assertion Mining Algorithms in GoldMine

GoldMine automatically generates assertions for register transfer level (RTL) designs using a combination of static analysis and machine learning algorithms. We compare four different machine learning algorithms implemented in GoldMine with respect to metrics that determine quality of their results. Metrics include assertion complexity, coverage, expectedness, predictive accuracy, and number of assertions. We introduce a new statically guided assertion mining algorithm, the best-gain decision forest (BGDF) algorithm here. In our comparative study, two of the algorithms have been invented by us for assertion generation, while the two others are standard machine learning algorithms. The best-gain decision forest and coverage guided association mining algorithms developed by us are compared with the decision tree and PRISM algorithms. We provide an extensive comparative study of assertion mining algorithms with experimental results on realistic designs. We also hereby provide access to these implementations in GoldMine that can be downloaded from [64] for research purposes.
Shobha Vasudevan, Lingyi Liu, Samuel Hertz

Chapter 21. Energy-Efficient Design of Advanced Machine Learning Hardware

The exponentially growing rates of data production in the current era of internet of things (IoT), cyber-physical systems (CPS), and big data pose ever-increasing demands for massive data processing, storage, and transmission. Such systems are required to be robust, intelligent, and self-learning while possessing the capabilities of high-performance and power-/energy-efficient systems. As a result, a hype in the artificial intelligence and machine learning research has surfaced in numerous communities (e.g., deep learning and hardware architecture).
This chapter first provides a brief overview of machine learning and neural networks followed by few of the most prominent techniques that have been used so far for designing energy-efficient accelerators for machine learning algorithms, particularly related to deep neural networks. Inspired by the scalable effort principles of human brains (i.e., scaling computing effort for required precision of the task, or for the recurrent execution of same/similar tasks), we focus on the (re-)emerging area of approximate computing (aka InExact Computing) which aims at relaxing the bounds of precise/exact computing to provide new opportunities for improving the area, power/energy, and performance efficiency of systems by orders of magnitude at the cost of reduced output quality. We also guide through a holistic methodology that encompasses the complete design phase, i.e., from algorithm to architectures. At the end, we summarize the challenges and the associated research roadmap that can aid in developing energy-efficient and adaptable hardware accelerators for machine learning.
Muhammad Abdullah Hanif, Rehan Hafiz, Muhammad Usama Javed, Semeen Rehman, Muhammad Shafique


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