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This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error.

After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
With the rapid development of the people’s demands for mobile communication in their daily life, the complex data communication and processing will become an important challenge to the future mobile communication. As the key part of the developing mobile communication technology, massive multiple-input multiple-output (MIMO) technology can improve the network capacity, enhance the network robustness and reduce the communication delay. However, as the number of antennas increases, so does the baseband processing complexity dramatically. The very large scale integration (VLSI) chip is the carrier of the massive antenna detection algorithm. The design of the massive MIMO baseband processing chip will become one of the bottlenecks in the real application of this technology, especially the design of massive MIMO detection chip with high complexity and low parallelism. The traditional MIMO detection processors, including the instruction set architecture processor (ISAP) and the application specific integrated circuit (ASIC), cannot simultaneously satisfy the three requirement indexes: energy efficiency, flexibility and scalability. In summary, the reconfigurable processor with the MIMO detection function can properly balance the requirements applied in sucs aspects as energy efficiency, flexibility and scalability, and it will be an important and promising development direction in the future.
Leibo Liu, Guiqiang Peng, Shaojun Wei

Chapter 2. Linear Massive MIMO Detection Algorithm

Abstract
Massive MIMO signal detection is the key technology of next generation wireless communication (such as 5G). In massive MIMO signal detection, there are many algorithms that can implement the signal detection. Generally, these algorithms can be divided into linear detection algorithm and nonlinear detection algorithm according to different calculation methods. Although the linear detection algorithm is less accurate than the nonlinear detection algorithm, it is still an effective signal detection method of massive MIMO system in some cases due to its low complexity. This chapter introduces several typical linear iterative algorithms for massive MIMO signal detection. By these algorithms, the iterations between vectors or matrices can be effectively used to avoid direct inversion of large-scale matrices and reduce complexity of the linear detection algorithm. In the following sections, we will introduce Neumann series approximation (NSA) algorithm, the Chebyshev iteration algorithm, the Jacobi iteration algorithm and the Conjugate gradient (CG) algorithm respectively. And the optimization methods of the Chebyshev iteration algorithm, the Jacobi iteration algorithm and the Conjugate gradient algorithm are also introduced for better linear detection algorithms. In addition, this chapter also compares the complexity and accuracy of these algorithms with other massive MIMO signal detection algorithms.
Leibo Liu, Guiqiang Peng, Shaojun Wei

Chapter 3. Architecture of Linear Massive MIMO Detection

Abstract
In practical massive MIMO detection, besides the influence of the algorithm’s own characteristics on the detection results, the hardware circuits also affect the efficiency of signal detection. In Chap. 2, we have introduced four typical iteration algorithms of massive MIMO linear detection, and illustrate their advantages by comparing them with some existing linear detection algorithms. This chapter describes how to implement the four algorithms in VLSI. First, it describes the implementation of the algorithms in the hardware circuits, and the matters needing attention. Then, it introduces the optimization problems in the chip design, including how to improve the throughput of chip, and how to reduce the power consumption and area of chip. Finally, the parameters of the designed chip are compared with those of the existing linear detection algorithms, and then the comprehensive comparison results are obtained.
Leibo Liu, Guiqiang Peng, Shaojun Wei

Chapter 4. Nonlinear Massive MIMO Signal Detection Algorithm

Abstract
This chapter first introduces several conventional nonlinear MIMO signal detection algorithms in Sect. 4.1. The optimal nonlinear ML signal detection algorithm is introduced first, and then the SD signal detection algorithm and the K-Best signal detection algorithm evolved from the nonlinear ML signal detection algorithm are introduced. Section 4.2 presents a K-best signal detection and preprocessing algorithm in high-order MIMO systems, combining the Cholesky sorted QR decomposition and partial iterative lattice reduction (CHOSLAR). At the same time, the algorithm uses the partial iterative lattice reduction (PILR) algorithm to acquire more asymptotically orthogonal matrix R. After the preprocessing, the K-Best signal detector combined with ordering reduction and branch expansion can achieve the detection accuracy similar to that of ML signal detection algorithm. Section 4.3 presents another new signal detection algorithm, TASER algorithm. Based on semi-definite relaxation, the TASER algorithm can achieve the signal detection performance of approximate ML within the computational complexity of the polynomial (with the number of transmitting antennas or time slots as independent variables) in the system with low bit rate and fixed modulation scheme.
Leibo Liu, Guiqiang Peng, Shaojun Wei

Chapter 5. Architecture for Nonlinear Massive MIMO Detection

Abstract
When the algorithm is mapped onto the corresponding hardware architecture design, people need to evaluate the performance of the hardware architecture such as data throughput, area, power consumption and delay, and research the resources reuse, the sub-module design and the whole module pipeline of the hardware architecture. The results of the linear algorithm in the hardware design aspect are not ideal due to the characteristics of the algorithm itself, so it is necessary to try to design the hardware architecture for the nonlinear algorithm. First, based on the CHOSLAR algorithm in Sect. 4.​2, we will design a VLSI architecture with K-best detection preprocessor for the 64 QAM modulation and the 16 × 16 MIMO system in this chapter. Experimental results show that this architecture has great advantages over the existing designs in data throughput, latency, energy efficiency (throughput/power) and area (throughput/gate number). Then, the corresponding systolic array is designed according to the TASER algorithm. The systolic array can realize high-throughput data detection with a lower silicon area. VLSI is implemented with Xilinx virtex-7 FPGA and the 40 nm CMOS technology, and the performance and computational complexity is compared in detail with that of other data detectors recently proposed for the massive MU-MIMO wireless system.
Leibo Liu, Guiqiang Peng, Shaojun Wei

Chapter 6. Dynamic Reconfigurable Chips for Massive MIMO Detection

Abstract
The contents of the dynamic reconfigurable chip design for detecting massive multiple-input multiple-output (MIMO) signals mainly involve the signal detection algorithm and model analysis and the reconfigurable signal detection and processing architecture design. The analysis of the signal detection algorithm mainly involves the behavior pattern analysis and parallelism of the mainstream signal detection algorithm the operator extraction and the operator frequency statistics. According to the detection algorithm features for massive MIMO signals, Sect. 6.1 analyzes the linear signal detection algorithms and the nonlinear signal detection algorithms. The reconfigurable detection processor for massive MIMO signals is customized for massive MIMO signal detection on the basis of the general reconfigurable computing architecture. Section 6.2 introduces relevant contents. One of the core advantages of the reconfigurable massive MIMO signal detection processor is that dynamic configuration is employed to meet the requirement of the massive MIMO signal detection application for flexibility. Section 6.3 introduce the reconfigurable configuration method and the configuration package design method.
Leibo Liu, Guiqiang Peng, Shaojun Wei

Chapter 7. Prospect of the VLSI Architecture for Massive MIMO Detection

Abstract
With respect to the manufacturing industry, in the 5G times, apart from intelligent terminals, the background network equipment of the 5G technology will encounter revolutionary changes as well. In this era, the network equipment manufacturing industry is no longer proprietary for conventional communications equipment manufacturers. Manufacturers who provide open computation equipment, storage equipment, and network equipment can also participate in the competition. To satisfy both the scalability and ultra-low delay requirements of computing capability on terminal devices, the new rising mobile edge computing (MEC) technology emerges as a promising paradigm in 5G communications. The basic thought of MEC is to offload cloud computing platform to the edge of mobile access network to enable the user equipment to offload computation tasks to the nodes at the edge of network, which is beneficial for 5G services to fulfill technical indicators such as ultra-low delay, ultra-high energy efficiency, and ultra-high reliability. This chapter probes into the future application scenarios and hardware development from three aspects: server, mobile terminal, and edge computing, which correspond to the subsequent sections.
Leibo Liu, Guiqiang Peng, Shaojun Wei
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