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Erschienen in:
Introduction to 3D Microelectronic Packaging Kapitel lesen Erstes Kapitel lesen

2017 | OriginalPaper | Buchkapitel

3. Materials and Processing of TSV

verfasst von : Praveen Kumar, Indranath Dutta, Zhiheng Huang, Paul Conway

Erschienen in: 3D Microelectronic Packaging

Verlag: Springer International Publishing

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Abstract

This chapter introduces the critical steps involved in fabricating through-silicon vias (TSVs) and associated materials. The fabrication steps for TSVs begin with etching of high aspect ratio trenches in Si, followed by placement of dielectric, barrier and seed layers, TSV filling and polishing, and then assembly with other components of a device. In addition, planarization, die-thinning and flow processes to fabricate TSV-enabled 3-D architectured microelectronic package are described. Challenges associated with processing of TSVs as well as methods for overcoming them are highlighted and discussed.

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Vorheriges Kapitel 3D Packaging Architectures and Assembly Process Design
Nächstes Kapitel Microstructural and Reliability Issues of TSV
Fußnoten
1
Layout efficiency is understood as the number of conductors per unit area.
 
2
KOZ is the region where functional properties of Si are significantly affected by the stress field of the TSV.
 
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Metadaten
Titel
Materials and Processing of TSV
verfasst von
Praveen Kumar
Indranath Dutta
Zhiheng Huang
Paul Conway
Copyright-Jahr
2017
Buch
3D Microelectronic Packaging

Print ISBN: 978-3-319-44584-7

Electronic ISBN: 978-3-319-44586-1

Copyright-Jahr: 2017

DOI
https://doi.org/10.1007/978-3-319-44586-1_3

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