Materials for Advanced Packaging

Three-dimensional (3D) integration, which can stack different materials, technologies, and functional components vertically, is a promising technology to overcome some physical, technological, and economic limits encountered in planar integrated circuits, extending Moore’s Law and enabling “More than Moore” applications. This chapter provides an overview of 3D integration technology, including review on its enabling technologies and the associated materials. The focus in this chapter is on the current development status and recent advances in materials, processes, and applications of the 3D integration technology.

This chapter covers six major bonding and joining techniques including adhesive bonding techniques, lead-free soldering processes, silver–indium bonding processes for high temperature applications, solid-state bonding technology, silver flip-chip interconnect technology, and 10 μm sliver flip-chip joints made by 250 °C solid-state bonding processes.

For adhesive bonding, four popular adhesives, epoxy resins, silicon resins, polymides, and acrylics, are reviewed. Two new adhesives, liquid crystal polymer (LCP) and SU8, are covered too. LCP has the properties of both polymers and liquid crystals. It, thus, can be bonded to silicon, metal, and glass and used as flexible circuit board.

In lead-free soldering, fundamental soldering principle is presented. To eliminate the use of fluxes, oxidation-free fluxless soldering was developed. It has been applied to developing numerous soldering processes based on systems such as Sn-Au, Sn-Cu, Sn-Ag, In-Au, In-Cu, and In-Ag. Two fluxless processes are reported. One is bonding between Si/Cr/Au/Sn/Ag and Si/Cr/Au. The other is between Si/Cr/Au and Al/Cr/Cu. Resulting joints are Sn with a little Ag. High bonding quality is achieved without using any flux. For the second process, the joints are strong despite the huge CTE mismatch between Si and Al.

In solid-state bonding technology, the bonding principle and a new quantum bonding theory are presented. Processes of bonding Cu with Ag layer to Cu substrates is reported, including shear test results and failure mode analyses.

Ag-In bonding is made between Si chips and Cu substrates at 180 °C. The joints consist of Ag/(Ag)/Ag₂In/(Ag)/Ag. Upon annealing at 190–250 °C, it can be converted to a single solid solution phase of (Ag). Samples could sustain 5000 thermal cycles between −40 and 200 °C, better than anything else. The resulting joints have a melting temperature of 800 °C.

In silver flip-chip interconnect, Ag columns fabricated on Si chips are bonded to Cu substrates at 250 °C with only 800 psi pressure. Nothing else is used. Composite columns of Cu/Ag, Ag/Au, and Cu/Au are also used with excellent results. Compared to solder-based flip-chip technique, our technology has 12 advantages. Compared to Cu pillar technique, our technology has much wider process window.

Most recent 10 μm Ag flip-chip process is introduced. It includes the development processes, pull strength results, and failure mode analyses.

Transistor scaling, shrinking the critical dimensions of the transistor, has led to continuous improvements in system performance and cost. Higher density of the transistors and larger chip size has also led to new challenges for chip-to-substrate connections. The pace of change in packaging and chip-to-substrate connections has accelerated because off-chip issues are increasingly a limiting factor in product cost and performance. Chip-to-substrate connections are challenged on many fronts, including number of signal input-output (I/O) connections, I/O that operate at high speed, power and ground I/O, and low cost.

This chapter examines various techniques and structures that have been designed to address these challenges. The mechanical compliance and electrical performance modeling of the interconnect structures is important in determining the geometry, materials, and processing necessary for an application. Various approaches have been taken to satisfy both the mechanical and electrical needs for these I/O connections. Mechanically compliant structures based on traditional solder-bonded connections can drastically improve thermomechanical reliability but may compromise electrical performance. Additional structures improve upon the compliance of the solder ball by capping a pillar structure with solder, but still require the reliable protection of underfill. More high performance and long-term improvements to satisfy both mechanical and electrical needs such as interconnects composed entirely of copper are also discussed. Finally, the future needs projected by the ITRS for ultra-high off-chip frequency and thermal management are addressed with respect to chip-to-substrate interconnects.

Wire bonding is by far the most dominate form of first-level chip connection. Around 85 % of the world’s electronic product is wire bonded representing over 15 trillion wire bonds on an annual basis. This chapter focuses on the basic techniques of wire bonding along with the materials, structures, and methods which enable its implementation. The emphasis is placed on ball bonding (thermosonic bonding) using both copper and gold bonding wire. Discussion of bonding machine parameters and various wire bond test methods are presented. Basic wire bond experimental studies are presented in some detail for two major purposes: (1) to highlight some of the key results of the experiments, and (2) to serve as a model for other researchers to either emulate or use as a starting point in their own wire bond investigations. Materials are fundamental to the reliability of wire bonding and where possible the author explores the major materials and material systems in some detail. Overall the chapter provides a frame work for the basic understanding of wire bonding for people new to the field as well as enough detailed information for the advanced practitioner.

Driven by RoHS regulation, the world has been migrating toward lead-free soldering since late 1990s. In this chapter, the main stream lead-free soldering practice was presented, and the properties of lead-free solder materials and soldering joints, including intermetallic compounds and microstructure evolution, were exemplified and discussed. Furthermore, the major categories of reliability of solder joints, including temperature cycling, fragility, electromigration, and tin whisker, were described and the mechanism was elucidated. Lastly, the trends and status of novel lead-free solder alloys, including low temperature, low cost and high reliability, and high temperature alloys were briefly introduced and reviewed.

Thin die fabrication is an essential part of wafer processes in 3D IC, interposer, and fan-in and fan-out wafer level packaging technologies. A review on the available process technologies including temporary bonding, de-bonding, wafer thinning, thin wafer handling, thin wafer backside processes, and die singulation are discussed and summarized in this chapter. The fabricated thin dies are integrated and assembled using wafer level system integration (WLSI) processes. A brief summary on two important WLSI technology platforms, namely Chip-on-Wafer-on-Substrate (CoWoS™) and Integrated Fan-Out (InFO) are presented as a conclusion for thin die fabrication and wafer level system integration chapter.

This chapter reviews materials and processing for fabricating organic substrates including laminate substrates for plastic BGA (PBGA), buildup substrates for flip chip BGA (FCBGA), tape substrates for tape BGA (TBGA), coreless substrates, and some specialty substrates such as substrates for RF modules, high performance substrates with low dielectric constant dielectrics, and substrate with embedded components (active dies and/or passives). Future trends of organic substrate development are covered in this chapter as well.

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermo-mechanical stress created by the Coefficient of Thermal Expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill material and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This chapter reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.

EMCs (Epoxy molding compounds) have been used extensively as an encapsulation and protection material for semiconductor packages. As semiconductor packages trend toward thinner, miniaturized, more function, and higher density, new requirements for EMCs are emerging. This chapter provides an overview of the most recent development on various aspects of EMC technology including advanced material development, molding process, and approaches to address different kinds of advanced packages.

Conductive adhesives consist of conductive particles and polymeric matrix, and can provide both electrical and mechanical connections. Much advance on conductive adhesive technology has been made over the years. This chapter provides a comprehensive overview on the basic aspects, key applications in electronic packaging, and latest advances of both anisotropically conductive adhesives (ACAs) and isotropically conductive adhesives (ICAs).

This chapter outlines the strong correlation between developments in electronic packaging technologies and required properties of die attach materials. An overview of die attach materials is summarized with the trends in the market. Die attach paste, adhesive tape for a lead on chip (LOC), die attach film, and the prospects of advanced die attach film are described in each section. The technical requirements of the die attach materials, which include high purity, fast curing, low stress, high package crack resistance, and multi-chip packaging are discussed.

Die attach films have become the main stream of die attach materials owing to their excellent properties and reliability. The future of advanced die attach films is explained with the introduction of adhesive film with dicing/die attach dual functionality.

The effects of adhesive properties such as peel strength and water absorption to improve package crack resistance are reported in detail. The development of die attach films with micro-phase separation structure for multi-layered packaging process is reviewed. Evaluation of die attach materials for next generation packages is also introduced.

Increasing electronic device performance has historically been accompanied by increasing power and increasing on-chip power density both of which present a cooling challenge. Thermal interface material (TIM) plays a key role in reducing the package thermal resistance and the thermal resistance between the electronic device and the external cooling components. This chapter reviews the progress made in the TIM development in the past 5 years. Rheology-based modeling and design is discussed for the widely used polymeric TIMs. The recently emerging technology of nanoparticles and nanotubes is also discussed for TIM applications. This chapter also includes TIM testing methodology and concludes with suggestion for the future TIM development directions.

Emerging portable smart devices with more functionality demands high-performance, smaller, lighter, thinner, and cheaper electronic components. This is enabled by the transformation of today’s surface-mounted discrete passives such as resistors, capacitors, and inductors as thin films embedded in the package substrate or buildup layers. Such a trend would lead to miniaturized and more efficient power systems.

This chapter reviews the fundamentals of materials, designs, and processes for each of these thin-film passive component technologies, particularly focusing on power applications. It then describes the challenges and recent advances in each of these areas.

With the development of silicon carbide (SiC) high-power semiconductor devices, which have the advantages of lower power losses, higher efficiencies, higher thermal conductivities, and higher operational temperatures compared to traditional silicon-based power devices, the demand for high-temperature bonding materials is becoming extremely urgent. The transition liquid phase (TLP) method has been used to form intermetallic compounds (IMCs) to bond SiC devices, and the IMCs formed by the TLP method have been studied as replacements for traditional low-temperature solder materials. However, the long process times and the high process temperatures required by the TLP method significantly damage power integrated circuits (ICs), and unstable IMCs cause reliability problems in the service process. Recently, metal particle pastes have been developed for high-power devices application, and these pastes have proven to be a feasible means of achieving high performance.

A review of recent advances in the development of metal pastes for bonding technology is provided in this chapter. The basic bonding technology, fundamental concepts of metal pastes, and the fabrication processes of pastes are introduced. The effect of nano- and micro-Ag pastes on the performance and reliability of the obtained joints is addressed in detail. The development of copper (Cu) pastes and its various anti-oxidation strategies are also summarized. Some precautions and propositions improving the strength and reliability of joints are also presented. Finally, at the end of the chapter, the direct-bonding method based on metal films is also discussed. These contents can be mainly interesting for researchers working on high-power semiconductor devices.

Wafer level chip scale packaging (WL-CSP) based on redistribution is the key technology which is evolving to system in package (SiP) and heterogeneous integration (HI) extended by 3-D packaging using through silicon vias (TSV). Due to further miniaturization on the chip-level WLP (wafer level package), it has been expanded to FO-WLP (fan-out WLP) which uses a molding process to expand the die size for redistribution. Therefore, the original WLP process for WL-CSP using redistribution is now called FI-WLP (fan-in WLP). Materials and process technologies are key for a reliable WLP. It is not only the choice for the right polymer or metal but the interfaces could be even more critical like under bump metallurgy or the adhesion of polymers. This chapter focuses on the materials and processes for WLP which are the basic for most of all new 3-D integration technologies.

Microelectromechanical systems (MEMS) technology enables us to create different sensing and actuating devices integrated with microelectronic, optoelectronic, radiofrequency (RF), thermal, and mechanical devices for advanced microsystems. In all these systems that demand low cost and small size, MEMS packaging is usually a major consideration. The relationship between MEMS and packaging, however, is not limited to packaging of MEMS devices. MEMS devices can in fact be used to enhance packaging technologies for microelectronic, optoelectronic, and RF systems. In addition, packaging technologies can be applied to fabricate MEMS devices. Therefore, packaging and MEMS technologies are essential to integrate sensors and actuators with other components on a single system platform. There is a great opportunity to apply MEMS and packaging technologies to develop fully integrated micro/nanosystems for smartphones, wearable electronics, and Internet of Things (IoT).

This chapter addresses the materials for the first step of light-emitting diode (LED) packaging, i.e., LED die attach adhesives (DAAs) and other chip bonding materials. The most significant difference between conventional integrated-circuit (IC) chip DAAs and LED DAAs is that the optical role of LED DAAs becomes the most important factor in additional to the other functions of conventional DAAs, i.e., adhesion and reliability. Thus, the chapter addresses in details of the optical role and optical requirement of LED DAAs and other LED chip bonding materials, in additional to the other conventional aspects of DAAs.

The first section of this chapter will review the function of LED packaging, LED packages, and materials. In the second part, recent development on LED die bonding materials will be introduced. Optical adhesives of different thermal conductivities, adhesive films, eutectic solder pastes, low-temperature sintering silver pastes will be presented in this section. The third part of this chapter provides an overview of most recent advanced LED packaging technologies, including surface-mount device (SMD), chip on board (COB), flip-chip (FC), chip scale package (CSP), and wafer-level CSP packaging (WLCSP), and the interaction between packages and DAAs. Important packaging parameters and their influence on optical and thermal performance of LEDs are elucidated.

Medical devices cover a wide range of products and applications that can be as basic as a tongue press, or as complex as an implanted life-sustaining therapy delivery device such as an Implantable Pulse Generator (IPG), or Implantable Cardiac Defibrillator (ICD). This chapter will provide an overview of medical devices that have electronic content, and an in-depth review of implantable medical devices design, manufacturing, and reliability considerations. The authors will examine industry trends, discuss key design considerations, and provide a review of product development, manufacturing, and reliability considerations for implantable medical electronics.

Significant advances have been made to the flexible electronics in the past two decades. A thin-film transistor (TFT) backplane is a generic component in an active-matrix electronic surface. TFT backplane technologies which have been developed for the flexible electronics applications can be mainly categorized into (a) hydrogenated amorphous silicon TFTs, (b) low-temperature polycrystalline silicon TFTs, (c) oxide TFTs, and (d) organic TFTs. The TFT fabrication usually involves accurate registrations between device layers. To mitigate misalignment issues caused by the handling of compliant substrates, built-in stress of deposited films, and mismatch strains between the device layers and substrates, lamination-debonding or coat (deposit)-release approaches for direct fabrication and transfer technique are developed. To further reduce the fabrication cost and improve the throughput, roll-to-roll compatible and printable processes are adopted. Gravure printing, offset printing, and flexography printing are commonly used contact printing technologies. Microcontact printing, nanoimprint, and transfer printing are emerging printing methods, which are of particular interest for the flexible electronics based on inorganic monocrystalline semiconductors. Non-contact printing methods, such as screen printing, inkjet printing, and slot-die printing, have also been widely investigated for the fabrication of flexible electronics. Depending on the roles of the printed materials, printing processes can be divided into two types: subtractive and additive. A subtractive printing process is similar to the conventional photolithography process, except the etch-mask material is applied by a printing method. In an additive printing process, the material waste is greatly reduced via direct “writing” of functional materials.

This chapter provides a brief overview of metallization pastes and technologies for silicon solar cells. The first section presents a brief introduction to different types of silicon solar cells. The second section reviews the metallization pastes for front- and back-side electrodes including new remarkable development in silver pastes employing nano-frits; copper and copper alloy pastes; aluminum and aluminum alloy pastes; and advanced formation technologies of front- and back-side electrodes. Finally, an overview of solar cell module materials and manufacturing process will be given, as well as performance and reliability testing methodology.

This chapter summarizes the current state-of-the-art for semiconductor and optoelectronic device fabrication using Metal-assisted chemical Etching (MacEtch). It details MacEtch’s history, the physics and chemistry, processing considerations, and applications in device fabrication.

3D packaging with through silicon vias (TSVs) is one of the major enabling technologies for the next generation of electronic devices. The TSVs are commonly plugged with Cu for vertical interconnect. The introduction of massive Cu in the TSVs may cause device failure due to the fast diffusion of Cu to Si. In order to prevent the diffusion, an interfacial multilayer is usually deposited on the sidewall of TSVs between the plugged Cu and the bulk Si. This chapter discusses the effects of different layers of the interfacial multilayer on the copper diffusion. Four factors of the interfacial multilayer, including the roughness of the Si surface, the insulation layer, the barrier layer, and the Cu seed layer, are considered. The selected interfacial multilayers are Cu/Ti/SiO₂/Si, Cu/TaN/SiO₂/Si, and additional structures without an insulation layer and/or a barrier layer. The phenomenon of copper diffusion is characterized with the analysis of depth profiling and surface profiling. A design of experiment using Taguchi method is also introduced to analyze the influential rank of the four factors on the copper diffusion.