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Erschienen in:
Introduction to Hardware/Software Codesign Kapitel lesen Erstes Kapitel lesen

2017 | OriginalPaper | Buchkapitel

27. Microarchitecture-Level SoC Design

verfasst von : Young-Hwan Park, Amin Khajeh, Jun Yong Shin, Fadi Kurdahi, Ahmed Eltawil, Nikil Dutt

Erschienen in: Handbook of Hardware/Software Codesign

Verlag: Springer Netherlands

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Abstract

In this chapter we consider the issues related to integrating microarchitectural IP blocks into complex SoCs while satisfying performance, power, thermal, and reliability constraints. We first review different abstraction levels for SoC design that promote IP reuse, and which enable fast simulation for early functional validation of the SoC platform. Since SoCs must satisfy a multitude of interrelated constraints, we then present high-level power, thermal, and reliability models for predicting these constraints. These constraints are not unrelated and their interactions must be considered, modeled and evaluated. Once constraints are modeled, we must explore the design space trading off performance, power and reliability. Several case studies are presented illustrating how the design space can be explored across layers, and what modifications could be applied at design time and/or runtime to deal with reliability issues that may arise.

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Vorheriges Kapitel Memory-Aware Optimization of Embedded Software for Multiple Objectives
Nächstes Kapitel MAPS: A Software Development Environment for Embedded Multicore Applications
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Metadaten
Titel
Microarchitecture-Level SoC Design
verfasst von
Young-Hwan Park
Amin Khajeh
Jun Yong Shin
Fadi Kurdahi
Ahmed Eltawil
Nikil Dutt
Copyright-Jahr
2017
Verlag
Springer Netherlands
Buch
Handbook of Hardware/Software Codesign

Print ISBN: 978-94-017-7266-2

Electronic ISBN: 978-94-017-7267-9

Copyright-Jahr: 2017

DOI
https://doi.org/10.1007/978-94-017-7267-9_28

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