5. mm-Wave Dividers

The PLL is a key subsystems of any transceiver for wireless applications. In state-of-the-art fundamental mm-Wave PLL (both analog and digital) the first divider and oscillator run at the highest frequency, becoming the system bottleneck for noise, tuning-range, power consumption and yield under PVT variation (X. Yi et al. in IEEE J Solid-State Circuits 49(2);347–359 (2014) [1], (W. Wu et al. in IEEE J. Solid-State Circuits 49(5);1081–1096, 2014) [2]. It is therefore highly desirable to adopt robust low power solutions for the frequency divider, with possibly a large tuning capability to overcome the variation. Injection locked (IL) LC frequency dividers achieve the higher speed for a given power consumption but need one or even more on-chip inductors rising the complexity of the design and yielding a large area consumption for a limited locking range (LR) (Yamamoto and Fujishima in IEEE International Solid State Circuits Conference - Digest of Technical Papers, San Francisco, CA, 2006) [3], (Chen et al. in IEEE Trans. Microw. Theory Tech. 57(12);3060–3069, 2009) [4], (Yu et al. in IEEE Microw. Wirel. Compon. Lett. 22(2), 82–84, 2012) [5], (Wu in IEEE Trans. Circuits Syst. I Regul. Pap. 60(8);2001–2008, 2013) [6], (Katayama et al. in IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Sendai, 2015) [7]. Static CML dividers, on the other hand, are famous for the wide LR, but require a large power consumption to work at high speed, even if inductive peaking techniques are used (Li et al. in Proceedings of ESSCIRC, Seville, 2010) [8]. In (Ghilioni et al. in IEEE J. Solid-State Circuits 48(8);1842–1850, 2013) [9] an RC static divider based on CML dynamic latches with load modulation is proposed. This topology, derived by the traditional CML static one, improves the divider performance at high frequencies, leading to a low power tunable solution. This chapter is organized as follow. The basic concept of injection locking is revised in Sect. 5.1. This technique is particularly powerful and commonly adopted by many state-of-the-art high speed low power frequency dividers and multipliers. It is also useful to study the effect of coupled oscillators (such as quadrature VCOs) and the undesired effect of pulling between two VCOs running at different frequencies on the same chip and/or between the VCO and the power amplifier in a direct conversion transmitter (Razavi in IEEE J. Solid-State Circuits 39(9);1415–1424, 2004) [10], (Mirzaei et al. in IEEE J. Solid-State Circuits 42(9);1916–1932, 2007) [11], (Mirzaei et al. in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014) [12]. Section 5.2 recalls the most popular circuits used in state-of-the-art high speed dividers. The operation principle of each solution is briefly summarized and the design trade-offs are highlighted. Section 5.3 presents a systematic design methodology to maximize performance of RC static divider based on CML dynamic latches with load modulation in the frequency band from 60 to 90 GHz. A divide-by-4 prototype 28 nm bulk CMOS based on the proposed design techniques is fully characterized, demonstrating a measured operating range from 25 to 102 GHz, when drawing 2.81–5.64 mW from a 0.9 V supply.