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Über dieses Buch

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures.

In this dissertation, we study outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. This chapter first provides a general description of NoC architectures. Then, it describes a generic synthesis flow for NoCs starting from the application specification through tape-out and applications. Finally, it addresses the interactions among these research problems and put the NoC design process into perspective.
Umit Y. Ogras, Radu Marculescu

Chapter 2. Literature Survey

Abstract
One of the most important reasons for using NoC architectures is their promise for scalability. Several books provide an introduction to the NoC concept and discuss various research issues, while an exhaustive list of references can be found in some NoC bibliographies available on-line. Likewise, a comprehensive introduction to NoCs and existing design practices is presented. In what follows, we provide a systematic literature review which is structured along the lines discussed.
Umit Y. Ogras, Radu Marculescu

Chapter 3. Motivational Example: MPEG-2 Encoder Design

Abstract
While NoCs gained recently a significant momentum, there are few NoC implementations of real applications reported to date. In this chapter, we present an MPEG-2 encoder using the NoC approach and compare it against the P2P and non-segmented bus-based designs running the same application. The MPEG-2 encoder has been selected as driver application since it covers a rich class of multimedia applications where similar considerations apply from an implementation standpoint.
Umit Y. Ogras, Radu Marculescu

Chapter 4. Target NoC Platform

Abstract
This chapter provides an overview of the network-on-chip architecture and application models utilized in this book. We first describe the target NoC platform and list our basic assumptions. Then, we present the NoC architecture and application models employed throughout the book. Finally, we conclude this chapter by discussing the technology implications on networks-on-chip design.
Umit Y. Ogras, Radu Marculescu

Chapter 5. NoC Performance Analysis

Abstract
Traditionally, performance evaluation of networks-on-chip (NoC) is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters can affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. This chapter presents a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The model presented in this chapter can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.
Umit Y. Ogras, Radu Marculescu

Chapter 6. Application-Specific NoC Architecture Customization Using Long-Range Links

Abstract
Networks-on-chip (NoC) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered in the literature are based on either completely regular or fully customized topologies. This chapter presents a methodology to automatically synthesize an architecture which is neither regular, nor fully customized. Instead, the resulting communication architecture is a superposition of a standard mesh network and a few long-range links which induce small world effects. Indeed, the few application-specific longrange links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization.
Umit Y. Ogras, Radu Marculescu

Chapter 7. Analysis and Optimization of Prediction-Based Flow Control in Networks-on-Chip

Abstract
While networks-on-Chip (NoC) architectures may offer higher bandwidth compared to traditional bus-based communication, their performance can degrade significantly in the absence of effective flow control algorithms. This chapter presents a predictive closed-loop flow control mechanism, which is used to predict the congestion level in the network. Based on this information, the proposed scheme controls the packet injection rate at traffic sources in order to regulate the total number of packets in the network. Finally, simulations and experimental study using our FPGA prototype show that the proposed controller delivers a better performance compared to the traditional switch-to-switch flow control algorithms under various real and synthetic traffic patterns.
Umit Y. Ogras, Radu Marculescu

Chapter 8. Design and Management of VFI Partitioned Networks-on-Chip

Abstract
The design of many core systems-on-chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption, and clock distribution problems. To deal with these issues, this chapter considers network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) and propose a design methodology for runtime energy management. The proposed approach minimizes the energy consumption subject to performance constraints. Then, we present efficient techniques for on-the-fly workload monitoring and management to ensure that the system can cope with variability in the workload and various technology-related parameters. Finally, the results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.
Umit Y. Ogras, Radu Marculescu

Chapter 9. Conclusion

Abstract
Continuous technology scaling will soon enable multicore designs with thousands of communicating IP blocks on a single chip. Successful design of systems at this scale will depend critically on truly scalable communication architectures. The promising solution to date is given by the structured communication via the NoC approach.
Umit Y. Ogras, Radu Marculescu

Backmatter

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