Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Bücher
Zeitschriften
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
SLX-Digitalkonferenz: Zukunftswerkstatt 2024

Mehr Umsatz mit Top-Kontakten

Am 7. Mai erfahren Sie, wie Vertriebsteams Leadgenerierung, Leadnurturing und Leadstrategien effizient steuern können.
Erweiterte Suche
Anmelden
nach oben
Erschienen in:
Basic Statistical Concepts Kapitel lesen Erstes Kapitel lesen

2006 | OriginalPaper | Buchkapitel

9. Modeling and Analyzing Yield, Burn-In and Reliability for Semiconductor Manufacturing: Overview

verfasst von : Way Kuo, Kyungmee Kim, Taeho Kim

Erschienen in: Springer Handbook of Engineering Statistics

Verlag: Springer London

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

The demand for proactive techniques to model yield and reliability and to deal with various infant mortality issues are growing with increased integrated circuit (IC) complexity and new technologies toward the nanoscale. This chapter provides an overview of modeling and analysis of yield and reliability with an additional burn-in step as a fundamental means for yield and reliability enhancement.
After the introduction, the second section reviews yield modeling. The notions of various yield components are introduced. The existing models, such as the Poisson model, compound Poisson models and other approaches for yield modeling, are introduced. In addition to the critical area and defect size distributions on the wafers, key factors for accurate yield modeling are also examined. This section addresses the issues in improving semiconductor yield including how clustering may affect yield.
The third section reviews reliability aspects of semiconductors such as the properties of failure mechanisms and the typical bathtub failure rate curve with an emphasis on the high rate of early failures. The issues for reliability improvement are addressed.
The fourth section discusses several issues related to burn-in. The necessity for and effects of burn-in are examined. Strategies for the level and type of burn-in are examined. The literature on optimal burn-in policy is reviewed. Often percentile residual life can be a good measure of performance in addition to the failure rate or reliability commonly used.
The fifth section introduces proactive methods of estimating semiconductor reliability from yield information using yield–reliability relation models. Time-dependent and -independent models are discussed.
The last section concludes this chapter and addresses topics for future research and development.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Jetzt informieren
Vorheriges Kapitel Stationary Marked Point Processes
Nächstes Kapitel Statistical Methods for Quality and Productivity Improvement
Literatur
9.1.
Semiconductor Industry Association: The National Technology Roadmap for Semiconductors (Semiconductor Industry, San Jose, CA 2003)
9.2.
World Semiconductor Trade Statistics: Semiconductor Market Forecast (Miyazaki, Japan May 2004)
9.3.
W. T. K. Chien, W. Kuo: Use of the Dirichlet process for reliability analysis, Comput. Ind. Eng. 27, 339–343 (1994)CrossRef
9.4.
W. T. K. Chien, W. Kuo: Extensions of Kaplan–Meier estimator, Commun. Stat. Simul. Comp. 24, 953–964 (1995)MATHCrossRef
9.5.
National Research Council Committee: Implications of Emerging Micro- and Nano-technologies, National Research Council Committee, Division of Engineering and Physical Sciences (National Academy, Washington 2003) p. 251
9.6.
W. Luo, Y. Kuo, W. Kuo: Dielectric relaxation and breakdown detection of doped tantalum oxide high-k thin films, IEEE Trans. Dev. Mater. Reliab. 4, 488–494 (2004)CrossRef
9.7.
W. Kuo, W. T. K. Chien, T. Kim: Reliability, Yield, and Stress Burn-in (Kluwer Academic, Norwell 1998)CrossRef
9.8.
C. J. McDonald: New tools for yield improvement in integrated circuit manufacturing: can they be applied to reliability, Microelectron. Reliab. 39, 731–739 (1999)CrossRef
9.9.
L. Peters: Introduction to Integrated Yield Analysis, Semicond. Int. 22, 56 (January 1999)
9.10.
http://www.cadence.com/whitepapers/5047/ParametricYieldWPfnl.pdf
9.11.
R. K. Ravikumar: Viewpoint addressing design yield prior to silicon, Chip Des. Mag. 40 (April/May 2004)
9.12.
A. M. Nardi, A. Sangiovanni-Vincentelli: Logic synthesis for manufacturability, IEEE Des. Test Comput. 21(3), 192–199 (2004)CrossRef
9.13.
A. J. Strojwas: Yield of VLSI Circuits: myths vs. reality, 23th Design Automation Conference (IEEE Computer Society, Las Vegas, NV 1986) pp. 234–235
9.14.
C. H. Stapper: Large area fault clusters and fault tolerance in VLSI circuits: a review, IBM J. Res. Develop. 33, 174–177 (1989)CrossRef
9.15.
W. Kuo, T. H. Kim: An overview of manufacturing yield and reliability modeling for semiconductor products, Proc. IEEE 87, 1329–1344 (1999)CrossRef
9.16.
A. V. Ferris-Prabhu: Introduction to Semiconductor Device Yield Modeling (Artech House, Boston 1992)
9.17.
T. L. Michalka, R. C. Varshney, J. D. Meindl: A discussion of yield modeling with defect clustering, circuit repair and circuit redundancy, IEEE Trans. Semicond. Manuf. 3, 116–127 (1990)CrossRef
9.18.
T. S. Barnett, A. D. Singh, V. P. Nelson: Estimating burn-in fall-out for redundacy memory, Proc. 2001 VLSI Test Symp. (IEEE Computer Society, Los Angeles, CA May 2001) pp. 340–347
9.19.
T. S. Barnett, A. D. Singh, V. P. Nelson: Extending integrated-circuit yield models to estimate early life reliability, IEEE Trans. Reliab. 52, 296–301 (2003)CrossRef
9.20.
T. S. Barnett, A. D. Singh, M. Grady, V. P. Nelson: Yield–reliability modeling: experimental verification and application to burn-in reduction, Proc. 20th IEEE VLSI Test Symp. (IEEE Computer Society, Monterey, CA 2002) pp. 1–6
9.21.
T. S. Barnett, M. Grady, K. Purdy, A. D. Singh: Redundancy implications for early-life reliability: experimental verification of an integrated yield–reliability model. In: ITC International Test Conference (IEEE Computer Society, Baltimore, MD 2002) pp. 693–699
9.22.
T. S. Barnett, A. D. Singh: Relating yield models to burn-in fall-out in time, ITC Int. Test Conf. (IEEE Computer Society, Charlotte, NC 2003) pp. 77–84
9.23.
H. H. Huston, C. P. Clarke: Reliability defect detection and screening during processing: theory and implementation, Proc. Int. Reliability Physics Symposium (IEEE Reliability Society, San Diego, CA 1992) pp. 268–275
9.24.
K. O. Kim, W. Kuo, W. Luo: A relation model of gate oxide yield and reliability, Microelectron. Reliab. 44, 425–434 (2004)CrossRef
9.25.
K. O. Kim, W. Kuo: A unified model incorporating yield, burn-in and reliability, Naval Res. Log. 51, 704–719 (2004)MathSciNetMATHCrossRef
9.26.
T. H. Kim, W. Kuo: Modeling manufacturing yield and reliability, IEEE Trans. Semicond. Manuf. 12, 485–492 (1999)CrossRef
9.27.
W. C. Riordan, R. Miller, J. Hicks: Reliability versus yield and die location in advanced VLSI, Microelectron. Reliab. 39, 741–749 (1999)CrossRef
9.28.
J. A. Cunningham: The use and evaluation of yield models in integrated circuit manufacturing, IEEE Trans. Semicond. Manuf. 3, 60–71 (1990)CrossRef
9.29.
M. Raghavachari, A. Srinivasan, P. Sullo: Poisson mixture yield models for integrated circuits: a critical review, Microelectron. Reliab. 37, 565–580 (1997)CrossRef
9.30.
R. E. Langford, J. J. Liou: Negative binomial yield model parameter extraction using wafer probe bin map data (IEEE Electron Devices Meeting, Hong Kong 1998) pp. 130–133
9.31.
F. Jensen: Yield, quality and reliability – a natural correlation?, Reliability 1991, ed. by R. H. Matthews (Elsevier Applied Science, London 1993) pp. 739–750
9.32.
Z. Stamenkovic, N. Stojadinovic: New defect size distribution function for estimation of chip critical area in integrated circuit yield models, Electron. Lett. 28, 528–530 (1992)CrossRef
9.33.
Z. Stamenkovic, N. Stojadinovic: Chip yield modeling related to photolithographic defects, Microelectron. Reliab. 32, 663–668 (1992)CrossRef
9.34.
G. Allen, A. Walton, R. Holwill: A yield improvement technique for IC layout using local design rules, IEEE Trans. CAD ICs Syst. 11, 1355–1362 (1992)
9.35.
S. Williamson, A. Singh, V. Nelson: Fault and yield modeling of MCMs for automotive applications, Proc. Int. MCM Conf. (IEEE Society, Denver 1996) pp. 147–154
9.36.
J. Mattick, R. Kelsall, R. Miles: Improved critical area prediction by application of pattern recognition techniques, Microelectron. Reliab. 36, 1815–1818 (1996)CrossRef
9.37.
C. H. Stapper, R. J. Rosner: Integrated circuit yield management and yield analysis: development and implementation, IEEE Trans. 8, 95–102 (1995)
9.38.
J. Segal, L. Milor, Y. K. Peng: Reducing baseline defect density through modeling random defect-limited yield, Micro Mag. 18, 61–71 (2000)
9.39.
H. Sato, M. Ikota, A. Sugimoto, H. Masuda: A new defect distribution metrology with a consistent discrete exponential formula and its application, IEEE Trans. Semicond. Manuf. 12, 409–418 (1999)CrossRef
9.40.
K. S. Park, C. H. Jun: Semiconductor yield models using contagious distributions and their limiting forms, Comput. Eng. 42, 115–125 (2002)
9.41.
C. H. Jun, Y. Hong, Y. K. Kim, K. S. Park, H. Park: A simulation-based semiconductor chip yield model incorporating a new defect cluster index, Microelectron. Reliab. 39, 451–456 (1999)CrossRef
9.42.
J. A. Carrasco, V. Suñé: Combinatorial methods for the evaluation of yield and operational reliability of fault-tolerant systems-on-chip, Microelectron. Reliab. 44, 339–350 (2004)CrossRef
9.43.
M. Scheffler, D. Cottet, G. Tröster: A simplified yield modeling method for design rule trade-off in interconnection substrates, Microelectron. Reliab. 41, 861–869 (2001)CrossRef
9.44.
S. P. Cunningham, C. J. Spanos, K. Voros: Semiconductor yield improvement: results and best practices, IEEE Trans. Semicond. Manuf. 8, 103–109 (1995)CrossRef
9.45.
C. N. Berglund: A unified yield model incorporating both defect and parametric effects, IEEE Trans. Semicond. Manuf. 9, 447–454 (1996)CrossRef
9.46.
D. Dance, R. Jarvis: Using yield models to accelerate learning curve progress, IEEE Trans. Semi. Manuf. 5, 41–45 (1992)CrossRef
9.47.
L. Peters: Choosing the Best Yield Model for Your Product, Semicond. Int. 23, 52 (May 2000)
9.48.
X. Li, J. Strojwas, M. F. Antonelli: Holistic Yield Improvement Methodology, Semiconductor Fabtech 27(7), 257–265 (1998)
9.49.
L. Peters: Demystifying Design-for-Yield, Semicond. Int. 27, 42 (July 2004)
9.50.
A. Amerasekera, D. S. Campbell: Failure Mechanisms in Semiconductor Devices (Wiley, New York 1987)
9.51.
J. E. Vinson, J. J. Liou: Electrostatic discharge in semiconductor devices: overview, Proc. IEEE 86, 399–419 (1998)CrossRef
9.52.
N. Wan, K. Manning: Exceeding 60-year life expectancy from an electronic energy meter, Metering Asia Pac. Conf. (Kuala Lumpur, Malaysia 20-22 February 2001)
9.53.
W. W. Abadeer, A. Bagramian, D. W. Conkle, C. W. Griffin, E. Langois, B. F. Lloyd, R. P. Mallette, J. E. Massucco, J. M. McKenna, S. W. Mittl, P. H. Noel: Key measurements of ultrathin gate dielectric reliability and in-line monitoring, IBM J. Res. Devel. 43, 407–417 (1999)CrossRef
9.54.
C. Hu: Future CMOS scaling and reliability, Proc. IEEE 81, 682–689 (May 1993)CrossRef
9.55.
J. Stevenson, J. A. Nachlas: Microelectronics reliability prediction derived from component defect densities (Pro Annual Reliab. Maintainab. Sympos., Los Angeles, CA 1990) pp. 366–370
9.56.
R. Doyle, J. Barrett: Design for Reliability: a Focus on Electronics Assembly, Solder. Surf. Mount Technol. 9(3), 22–29 (1997)
9.57.
M. Baz, M. Udrea-Spenea, E. Tsoi, F. Turtudau, V. Ilian, G. Papaioannou, L. Galateanu, A. Stan, A. Tserepi, M. Bucur: Building in reliability technology for diodes manufacturing, IEEE CAS 2000 Proceedings 1, 333–337 (2000)
9.58.
W. T. K. Chien, C. H. J. Huang: Pracitical building in reliability approaches for semiconductor manufacturing, IEEE Trans. Reliab. 52, 469–482 (2002)
9.59.
S. Garrard: Production implementation of a practical WLR program (1994 IRW Final Report IEEE International, Lake Tahoe, CA 1995) pp. 20–29
9.60.
L. N. Lie, A. K. Kapoor: Wafer level reliability procedures to monitor gate oxide quality using V ramp and J ramp test methodology, 1995 IRW Final Report (IEEE International, Gold Canyon, AZ 1996) pp. 113–121
9.61.
A. P. Bieringer, D. Koch, H. Kammer, a. Kohlhase, A. Lill, A. Preusser, A. Schlemm, M. Schneegans: Implementation of a WLR—program into a production line (1995 IRW Final Report, Gold Canyon, AZ 1996) pp. 49–54
9.62.
T. A. Dellin, W. M. Miller, D. G. Pierce, E. S. Snyder: Wafer level reliability, SPIE Microelectron. Manuf. Reliab. 18(2), 144–154 (1992)
9.63.
J. M. Soden, R. E. Anderson: IC failure analysis: techniques and tools for quality and reliability improvement, Proc. IEEE 81, 703–715 (1993)CrossRef
9.64.
A. W. Righter, C. F. Hawkins, J. M. Soden, P. Maxwell: CMOS IC reliability indicators and burn-in economics (International Test Conference, IEEE Computer Society, Washington D.C. 1998) pp. 194–204
9.65.
W. Kuo, Y. Kuo: Facing the headaches of early failures: a state-of-the-art review of burn-in decisions, Proc. IEEE 71, 1257–1266 (1983)CrossRef
9.66.
A. Vassighi, O. Semenov, M. Sachdev: CMOS IC technology scaling and its impact on burn-in, IEEE Trans. Dev. Mater. Reliab. 4, 208–222 (2004)CrossRef
9.67.
D. Gralian: Next generation burn-in development, IEEE Trans. Components Packaging Manuf. Technol. 17, 190–196 (May 1994)CrossRef
9.68.
B. Vasquez, S. Lindsey: The promise of known-good-die technologies, MCM ʼ94 Proc. (IEEE Society, Santa Clara, CA 1994) pp. 1–6
9.69.
D. Inbar, M. Murin: KGD for flash memory: burn-in is key, Semicond. Int. 8, 1 (2004)
9.70.
A. Wager: Wafer probe tests and stresses used for quality and reliability improvement, 8th Annual KGD packaging and Test Workshop Proceedings (Die Products Consortium, Napa, CA September 2001)
9.71.
P. Garrou: The wafer level packaging evolution, Semicond. Int. 27, 119 (10/2/2004)
9.72.
R. Nelson: Hot tests whip chips into shape, Test Meas. World 20(12), 30 (October 2000)
9.73.
D. Romanchik: Why burn-in ICs ?, Test Measurement World 12, 85–88 (Oct. 1992)
9.74.
9.75.
J. Mi: minimizing some cost functions related to both burn-in and field use, Oper. Res. 44, 497–500 (1996)MATHCrossRef
9.76.
S. H. Sheu, Y. H. Chien: |Minimizing cost functions related to both burn-in and field operation under a generalized model, IEEE Trans. Reliab. 53, 435–440 (2004)CrossRef
9.77.
Kosznik, Drapella: Combining preventive replacements and burn-in procedures, Qual. Reliab. Eng. Int. 18, 423–427 (2002)CrossRef
9.78.
9.79.
9.80.
J. H. Cha, S. Lee, J. Mi: Bonding the optimal burn-in time for a system with two types of failure, Naval Res. Logist. 51, 1090–1101 (2004)MathSciNetMATHCrossRef
9.81.
S. T. Tseng, C. Y. Peng: Optimal burn-in policy by using an integrated Wiener process, IIE Trans. 36, 1161–1170 (2004)CrossRef
9.82.
K. N. Kim: Optimal burn-in for minimizing cost and multi-objectives, Microelectron. Reliab. 38, 1577–1583 (1998)CrossRef
9.83.
W. T. K. Chien, W. Kuo: A nonparametric approach to estimate system burn-in time, IEEE Trans. Semicond. Manuf. 9, 461–466 (1996)CrossRef
9.84.
W. T. K. Chien, W. Kuo: A nonparametric Bayes approach to decide system burn-in time, Naval Res. Logist. 44, 655–671 (1997)MathSciNetMATHCrossRef
9.85.
W. Kuo: Reliability enhancement through optimal burn-in, IEEE Trans. Reliab. R-33, 145–156 (1984)CrossRef
9.86.
D. H. Chi, W. Kuo: Burn-in optimization under reliability and capacity restrictions, IEEE Trans. Reliab. 38, 193–199 (1989)CrossRef
9.87.
T. R. Kar, J. A. Nachlas: Coordinated warranty & burn-in strategies, IEEE Trans. Reliab. 46, 512–519 (1997)CrossRef
9.88.
K. O. Kim, W. Kuo: Percentile residual life and system reliability as performance measures in the optimal system design, IIE Trans. 35, 1133–1142 (2003)CrossRef
9.89.
H. W. Block, J. Mi, T. H. Savits: Some results on burn-in, Stat. Sin. 4, 525–534 (1994)MathSciNetMATH
9.90.
H. W. Block, J. Mi, T. H. Savits: Burn-in at the component and system level. In: Lifetime Data: Models in Reliability and Survival Analysis, ed. by N. P. Jewell, A. C. Kimber, M. L. T. Lee, G. A. Whitmore (Kluwer, Dordrecht 1995)
9.91.
C. W. Whitbeck, L. M. Leemis: Component vs. system burn-in techniques for electronic equipment, IEEE Trans. Reliab. 38, 206–209 (1989)CrossRef
9.92.
R. K. Reddy, D. L. Dietrich: A 2-level environmental stress screening model: a mixed distribution approach, IEEE Trans. Reliab. 43, 85–90 (1994)CrossRef
9.93.
E. A. Pohl, D. L. Dietrich: Environmental stress screening strategies for multi-component systems with weibull failure times and imperfect failure detection (Proceedings Annual Reliability and Maintainability Symposium, Washington D.C. 1995) pp. 223–232
9.94.
W. Kuo: Incompatibility in evaluating large-scale systems reliability, IEEE Trans. Reliab. 43, 659–660 (1994)CrossRef
9.95.
W. T. K. Chien, W. Kuo: Modeling and maximizing burn-in effectiveness, IEEE Trans. Reliab. 44, 19–25 (1995)CrossRef
9.96.
W. T. K. Chien, W. Kuo: Optimal burn-in simulation on highly integrated circuit systems, IIE Trans. 24, 33–43 (1992)CrossRef
9.97.
T. H. Kim, W. Kuo: Optimal burn-in decision making, Qual. Reliab. Eng. Int. 14, 417–423 (1998)CrossRef
9.98.
K. O. Kim, W. Kuo: A general model of heterogeneous system lifetimes and conditions for system burn-in, Naval Res. Log. 50, 364–380 (2003)MathSciNetMATHCrossRef
9.99.
K. O. Kim, W. Kuo: Some considerations on system burn-in, IEEE Trans. Reliab. 54(2), 207–214 (2005)CrossRef
9.100.
K. O. Kim, W. Kuo: Two-level burn-in for reliability and economy in repairable series systems having incompatibility, J. Reliab. Qual. Saf. Eng. 11(3), 197–211 (2004)CrossRef
9.101.
F. Kuper, J. Vander Pol, E. Ooms, T. Johnson, R. Wijburg: Relation between yield and reliability of integrated circuits: experimental results and application to continuous early failure rate reduction programs (Proc. Int. Reliab. Phys. Symp., Dallas, Texas 1996) pp. 17–21
9.102.
J. Van der Pol, F. Kuper, E. Ooms: Relation between yield and reliability of ICs and application to failure rate assessment and reduction in the one digit fit and ppm reliability era, Microelectron. Reliab. 36, 1603–1610 (1996)CrossRef
9.103.
T. Zhao, Y. Hao, P. Ma, T. Chen: Relation between reliability and yield of ICs based on discrete defect distribution model, Proc. 2001 IEEE Int. Symp. Defect Fault Tolerance in VLSI systems (IEEE Society, San Francisco, CA 2001)
9.104.
J. Van der Pol, E. Ooms, T. Hof, F. Kuper: Impact of screening of latent defects at electrical test on yield-reliability relation and application to burn-in elimination (Int. Relia. Phys. Sympos., Reno, NV 1998) pp. 370–377
9.105.
K. R. Forbes, N. Arguello: Using time-dependent reliability fallout as a function of yield to optimize burn-in time for a 130nm SRAM device. In: Integ. Reliab. Workshop Final Rep., IEEE Int., Lake Tahoe, CA (IEEE Society 2003) pp. 61–66
9.106.
T. H. Kim, W. Kuo, K. Chien: Burn-in effect on yield, IEEE Trans. Electron. Pack. Manuf. 23, 293–299 (2000)CrossRef
9.107.
K. O. Kim, M. Zuo, W. Kuo: On the relationship of semiconductor yield and reliability, IEEE Trans. Semicond. Manuf. 18(3), 422–429 (2005)CrossRef
Metadaten
Titel
Modeling and Analyzing Yield, Burn-In and Reliability for Semiconductor Manufacturing: Overview
verfasst von
Way Kuo
Kyungmee Kim
Taeho Kim
Copyright-Jahr
2006
Buch
Springer Handbook of Engineering Statistics

Print ISBN: 978-1-85233-806-0

Electronic ISBN: 978-1-84628-288-1

Copyright-Jahr: 2006

DOI
https://doi.org/10.1007/978-1-84628-288-1_9

Neuer Inhalt

    Bildnachweise