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Erschienen in:
1997 | OriginalPaper | Buchkapitel
Modeling the Power Consumption of CMOS Arithmetic Elements
verfasst von : Thomas K. Callaway
Erschienen in: Application Specific Processors
Verlag: Springer US
Enthalten in: Professional Book Archive
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Designers are faced with the task of designing circuits and systems which must use minimum power dissipation. By providing the designer with accurate estimates of the power dissipation of CMOS adders and multipliers, this research aids in the initial circuit choice, thus reducing the number and length of the design iterations. Simulation and direct measurement of the performance of test chips is used to evaluate their characteristics, and the results are used to rank the circuits on dynamic power dissipation.