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2020 | OriginalPaper | Buchkapitel

Multi Header Based Ultra Low Power MTCMOS Technique to Reduce NBTI Effect in Combinational Circuit

verfasst von : Anjan Kumar, Shelesh Krishna Saraswat, Preeti Agrawal, Shweta Singh

Erschienen in: 4th International Conference on Internet of Things and Connected Technologies (ICIoTCT), 2019

Verlag: Springer International Publishing

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Abstract

With the advancement of technology, negative bias temperature instability (NBTI) emerges out as a major problem for VLSI circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues present extreme unwavering quality issues for CMOS devices. Since both the NBTI and leakage are reliant on input test vector of the circuit however input vector control strategy isn’t viable for bigger circuits. Thus in this paper two design is proposed (1) Single header Based Ultra low Power Diode Tri-mode Technique is designed for reducing leakage and delay of the circuit (2) Multi header Based Ultra low Power Diode Tri mode Technique with Body Bias on all sleep pMOS transistor to mitigate NBTI effect. Experimentations are done on 1 bit full adder circuit with the usage of tanner EDA at 90 nm CMOS technology node and supply voltage 1 V. The results reveal that by using first proposed technique leakage current is reduces by 74.93% and 0.217% respectively as compare to Stacking with delay based MTCMOS method and ULP diode based MTCMOS method. First proposed design is also effective in terms of delay. Result shows that delay get reduced by 20.91% and 7.84% as compare to prevalent techniques. Second Proposed design at 50% Duty cycle is very much effective for NBTI effect mitigation. Experimental result shows that Second Proposed design with reduction in duty cycle(from 100% to 50%) the Vth shift on pMOS transistor reduces and with this decrement in Vth of pMOS transistor NBTI effect on the circuit will get reduced.

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Literatur
1.
Zurück zum Zitat Narendra, S.G., Chandrakasan, A.P.: Leakage in Nanometer CMOS Technologies. Springer Science & Business Media (2006) Narendra, S.G., Chandrakasan, A.P.: Leakage in Nanometer CMOS Technologies. Springer Science & Business Media (2006)
2.
Zurück zum Zitat Calimera, A., Macii, E., Poncino, M.: Design techniques for nbti-tolerant power-gating architectures. IEEE Trans. Circ. Syst. II: Express Briefs 59(4), 249–253 (2012) Calimera, A., Macii, E., Poncino, M.: Design techniques for nbti-tolerant power-gating architectures. IEEE Trans. Circ. Syst. II: Express Briefs 59(4), 249–253 (2012)
3.
Zurück zum Zitat Ravindra, N.M.: International technology roadmap for semiconductors (İTRS). J. Electron. Mater. 30(12), 1478–1627 (2001). SymposiumCrossRef Ravindra, N.M.: International technology roadmap for semiconductors (İTRS). J. Electron. Mater. 30(12), 1478–1627 (2001). SymposiumCrossRef
4.
Zurück zum Zitat Pattanaik, M., Agnihotri, S., Varaprashad, M.V.D.L., Arasu, T.A.: Enhanced ground bounce noise reduction in a low leakage 90 nm 1-volt cmos full adder cell. In: 2010 International Symposium on Electronic System Design (ISED), pp. 175–180. IEEE (2010) Pattanaik, M., Agnihotri, S., Varaprashad, M.V.D.L., Arasu, T.A.: Enhanced ground bounce noise reduction in a low leakage 90 nm 1-volt cmos full adder cell. In: 2010 International Symposium on Electronic System Design (ISED), pp. 175–180. IEEE (2010)
5.
Zurück zum Zitat Deepaksubramanyan, B.S., Nunez, A.: Analysis of subthresh-old leakage reduction in cmos digital circuits. In: 50th Midwest Symposium on Circuits and Systems, 2007, MWSCAS 2007, pp. 1400–1404. IEEE (2007) Deepaksubramanyan, B.S., Nunez, A.: Analysis of subthresh-old leakage reduction in cmos digital circuits. In: 50th Midwest Symposium on Circuits and Systems, 2007, MWSCAS 2007, pp. 1400–1404. IEEE (2007)
6.
Zurück zum Zitat Roy, S., Liu, D., Singh, J., Um, J., Pan, D.Z.: OSFA: a new paradigm of aging aware gate-sizing for power/performance optimizations under multiple operating conditions. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 35(10), 1618–1629 (2016)CrossRef Roy, S., Liu, D., Singh, J., Um, J., Pan, D.Z.: OSFA: a new paradigm of aging aware gate-sizing for power/performance optimizations under multiple operating conditions. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 35(10), 1618–1629 (2016)CrossRef
7.
Zurück zum Zitat Arya, N., Singh, S., Pattanaik, M.: Temperature insensitive design for power gated circuits. In: 2014 9th International Conference on Industrial and Information Systems (ICIIS), pp. 1–6, December 2014 Arya, N., Singh, S., Pattanaik, M.: Temperature insensitive design for power gated circuits. In: 2014 9th International Conference on Industrial and Information Systems (ICIIS), pp. 1–6, December 2014
8.
Zurück zum Zitat Sharma, S., Kumar, A., Pattanaik, M., Raj, B.: Forward body biased multimode multi-threshold cmos technique for ground bounce noise reduction in static cmos adders. Int. J. Inf. Electron. Eng. 3(6), 567 (2013) Sharma, S., Kumar, A., Pattanaik, M., Raj, B.: Forward body biased multimode multi-threshold cmos technique for ground bounce noise reduction in static cmos adders. Int. J. Inf. Electron. Eng. 3(6), 567 (2013)
9.
Zurück zum Zitat Jiao, H., Kursun, V.: How forward body bias helps to reduce ground bouncing noise and silicon area in mtcmos circuits: divulging the basic mechanism. In: SoC Design Conference (ISOCC), 2010 International, pp. 9–12. IEEE (2010) Jiao, H., Kursun, V.: How forward body bias helps to reduce ground bouncing noise and silicon area in mtcmos circuits: divulging the basic mechanism. In: SoC Design Conference (ISOCC), 2010 International, pp. 9–12. IEEE (2010)
10.
Zurück zum Zitat Calimera, A., Macii, E., Poncino, M.: NBTİ-aware power gating for concurrent leakage and aging optimization. In Proceedings of the 2009 ACM/IEEE İnternational Symposium on Low power Electronics and Design, pp. 127–132. ACM (2009) Calimera, A., Macii, E., Poncino, M.: NBTİ-aware power gating for concurrent leakage and aging optimization. In Proceedings of the 2009 ACM/IEEE İnternational Symposium on Low power Electronics and Design, pp. 127–132. ACM (2009)
11.
Zurück zum Zitat Ren, P., Liu, C., Wang, R., Gong, N., Liu, J., Wu, H., Huang, R.: New understanding on the single-trap response under nbti stress and the resulted stochastic degradation in nanoscale mosfets. In: 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, pp. 1–3, October 2012 Ren, P., Liu, C., Wang, R., Gong, N., Liu, J., Wu, H., Huang, R.: New understanding on the single-trap response under nbti stress and the resulted stochastic degradation in nanoscale mosfets. In: 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, pp. 1–3, October 2012
12.
Zurück zum Zitat Levacq, D., Dessard, V., Flandre, D.: Low leakage soi cmos static memory cell with ultra-low power diode. IEEE J. Solid-State Circ. 42(3), 689–702 (2007)CrossRef Levacq, D., Dessard, V., Flandre, D.: Low leakage soi cmos static memory cell with ultra-low power diode. IEEE J. Solid-State Circ. 42(3), 689–702 (2007)CrossRef
Metadaten
Titel
Multi Header Based Ultra Low Power MTCMOS Technique to Reduce NBTI Effect in Combinational Circuit
verfasst von
Anjan Kumar
Shelesh Krishna Saraswat
Preeti Agrawal
Shweta Singh
Copyright-Jahr
2020
DOI
https://doi.org/10.1007/978-3-030-39875-0_5