6. Multi-Task MIMO Signal Processing

Driven by the requirement of multi-dimensional computing in contemporary wireless communication technologies, reconfigurable platforms have come to the era of vector-based architectures. In this chapter, the reconfigurable cell array developed in Chaps. 4 and 5 is extended with extensive vector computing capabilities, aiming for high-throughput baseband processing in MIMO-OFDM systems. Besides the heterogeneous and hierarchical resource deployments, a vector-enhanced SIMD structure and various memory access schemes are employed. These architectural enhancements are designed to suffice stringent computational requirements while retaining high flexibility and hardware efficiency. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 mm² core area. To illustrate its performance and flexibility, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and symbol detection, of a 4 × 4 MIMO processing chain in a 20 MHz 64-QAM Long term evolution-advanced (LTE-A) downlink are mapped and processed in real-time. Operating at 500 MHz and 1.2 V voltage supply, the achieved throughput is 367.88 Mb/s and the average power consumption is 548.78 mW. The corresponding energy consumption for processing one information bit is 1.49 nJ. Comparing to state-of-the-art implementations, the presented solution outperforms related programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of area and energy efficiency to that of ASICs.