Multilayer Perceptron Algorithm: Impact of Nonideal Conductance and Area-Efficient Peripheral Circuits

Large arrays of the same nonvolatile memories (NVMs) being developed for storage-class memory (SCM) – such as phase-change memory (PCM) and resistive RAM (RRAM) – can also be used in non-Von Neumann neuromorphic computational schemes, with device conductance serving as synaptic “weight.” This allows the all-important multiply-accumulate operation within these algorithms to be performed efficiently at the weight data.In contrast to other groups working on spike-timing-dependent plasticity (STDP), we have been exploring the use of NVM and other inherently analog devices for artificial neural networks (ANN) trained with the backpropagation algorithm. We recently showed a large-scale (165,000 two-PCM synapses) hardware/software demo (IEDM 2014) and analyzed the potential speed and power advantages over GPU-based training (IEDM 2015).In this chapter, we extend this work in several useful directions. In order to develop an intuitive understanding of the impact that various features of such jump tables have on the classification performance in the ANN application, we describe studies of various artificially constructed jump tables. We then assess the impact of undesired, time-varying conductance change, including drift in PCM and leakage of analog CMOS capacitors. We investigate the use of nonfilamentary, bidirectional RRAM devices based on PrCaMnO₃, with an eye to developing material variants that provide sufficiently linear conductance change. And finally, we explore trade-offs in designing peripheral circuitry, balancing simplicity and area efficiency against the impact on ANN performance.