Skip to main content

2010 | OriginalPaper | Buchkapitel

15. NAND design for testability and testing

verfasst von : Andrea Silvagni

Erschienen in: Inside NAND Flash Memories

Verlag: Springer Netherlands

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

NAND business requires huge investments in technology developments and manufacturing. Moreover, leading edge NAND Flash memory costs and yield issues increase with every new technology node. Addressing test issues is mandatory for NAND Flash manufacturers to accelerate yield learning and enhancement, maintaining a competitive cost structure.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat K. Sakui and K-D Suh NAND Flash Memory Technology in the book Non Volatile Memories with Emphasis on Flash, p223, Wiley, 2008 K. Sakui and K-D Suh NAND Flash Memory Technology in the book Non Volatile Memories with Emphasis on Flash, p223, Wiley, 2008
2.
Zurück zum Zitat G. Casagrande, Flash Memories, Kluwer, 1999 G. Casagrande, Flash Memories, Kluwer, 1999
3.
Zurück zum Zitat A. Silvagni, G. Fusillo, R. Ravasio, M. Picca, S. Zanardi, An overview of logic architecture inside Flash memory devices, Proceedings of the IEEE, pp. 569–580, April 2003, Vol. 91 A. Silvagni, G. Fusillo, R. Ravasio, M. Picca, S. Zanardi, An overview of logic architecture inside Flash memory devices, Proceedings of the IEEE, pp. 569–580, April 2003, Vol. 91
4.
Zurück zum Zitat P. Cappelletti, A. Modelli, Flash Memory Reliability, in the book Flash Memories, Kluwer, 1999CrossRef P. Cappelletti, A. Modelli, Flash Memory Reliability, in the book Flash Memories, Kluwer, 1999CrossRef
6.
Zurück zum Zitat R. Micheloni, A. Marelli, R. Ravasio, Error Correction Codes for Non-Volatile Memories, Springer, 2008 R. Micheloni, A. Marelli, R. Ravasio, Error Correction Codes for Non-Volatile Memories, Springer, 2008
7.
Zurück zum Zitat M. Abramovici, M. A. Breuer, A. D. Friedman, Digital System testing and Testable Design, IEEE Press, 1990 M. Abramovici, M. A. Breuer, A. D. Friedman, Digital System testing and Testable Design, IEEE Press, 1990
8.
Zurück zum Zitat M.L. Buschnell, V.D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI, Kluwer, 2000 M.L. Buschnell, V.D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI, Kluwer, 2000
9.
Zurück zum Zitat P. Nicosia, F. Nava, Test Strategies on Non Volatile Memories, NVSMW, 2007. 22nd IEEE Volume, Issue, 26–30 Aug. 2007 Page(s):11–18 P. Nicosia, F. Nava, Test Strategies on Non Volatile Memories, NVSMW, 2007. 22nd IEEE Volume, Issue, 26–30 Aug. 2007 Page(s):11–18
11.
Zurück zum Zitat K. Hosono, T. Tanaka, K. Imamiya, K. Sakui, “A High speed Failure bit Counter for the Pseudo Pass Scheme in Program operation for Giga Bit NAND Flash”, Non-Volatile semiconductor Memory Workshop, 2003. K. Hosono, T. Tanaka, K. Imamiya, K. Sakui, “A High speed Failure bit Counter for the Pseudo Pass Scheme in Program operation for Giga Bit NAND Flash”, Non-Volatile semiconductor Memory Workshop, 2003.
12.
Zurück zum Zitat K. Takeuchi, T. Tanaka, T. Tanzawa, A Multipage cell Architecture for High-Speed Programming Multilevel NAND Flash memories. IEEE Journal of Solid state circuits, Vol. 33, NO. 8, Aug. K. Takeuchi, T. Tanaka, T. Tanzawa, A Multipage cell Architecture for High-Speed Programming Multilevel NAND Flash memories. IEEE Journal of Solid state circuits, Vol. 33, NO. 8, Aug.
13.
Zurück zum Zitat K. Imamiya, Y. Sugiura, Nakamura, T. Himeno, K. Takeuchi, T. Ikehashi, K. Kanda, K. Hosono, R. Shirota, S. Aritome, K. Shimizu, K. Hatakeyama, and K. Sakui, A 130-mm2 256-Mbit NAND Flash with shallow trench isolation technology. IEEE Journal of Solid state circuits, Vol. 34, NO. 11, Nov. 1999. K. Imamiya, Y. Sugiura, Nakamura, T. Himeno, K. Takeuchi, T. Ikehashi, K. Kanda, K. Hosono, R. Shirota, S. Aritome, K. Shimizu, K. Hatakeyama, and K. Sakui, A 130-mm2 256-Mbit NAND Flash with shallow trench isolation technology. IEEE Journal of Solid state circuits, Vol. 34, NO. 11, Nov. 1999.
14.
Zurück zum Zitat K. Takeuchi and T. Tanaka A Dual-Page Programming Scheme for High-Speed Multigigabit-Scale NAND Flash Memories. IEEE Journal of Solid state circuits, Vol. 36, NO. 5, May 2001. K. Takeuchi and T. Tanaka A Dual-Page Programming Scheme for High-Speed Multigigabit-Scale NAND Flash Memories. IEEE Journal of Solid state circuits, Vol. 36, NO. 5, May 2001.
15.
Zurück zum Zitat K. Imamiya et al, A 125-mm2 1-Gb NAND Flash Memory With 10-MByte/s Program Speed. IEEE Journal of Solid state circuits, Vol. 37, NO. 11, Nov 2002. K. Imamiya et al, A 125-mm2 1-Gb NAND Flash Memory With 10-MByte/s Program Speed. IEEE Journal of Solid state circuits, Vol. 37, NO. 11, Nov 2002.
16.
Zurück zum Zitat T. Hara et al., A 146-mm2 8-Gb Multi-Level NAND Flash Memory With 70-nm CMOS Technology IEEE Journal of Solid state circuits, Vol. 41, NO. 1, Jan 2006. T. Hara et al., A 146-mm2 8-Gb Multi-Level NAND Flash Memory With 70-nm CMOS Technology IEEE Journal of Solid state circuits, Vol. 41, NO. 1, Jan 2006.
17.
Zurück zum Zitat K. Park, J. Choi, J. Sel, V. Kim, Y. Shin and K. Kim, Scalable WL Shielding Scheme using Dummy Gates in NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell, 2006 International Conference on Solid State Devices and Materials, C-6-4L, 2006, pp. 298-299. K. Park, J. Choi, J. Sel, V. Kim, Y. Shin and K. Kim, Scalable WL Shielding Scheme using Dummy Gates in NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell, 2006 International Conference on Solid State Devices and Materials, C-6-4L, 2006, pp. 298-299.
18.
Zurück zum Zitat T. Tanzawa, T. Tanaka, K. Takeuchi, and H. Nakamura, Circuit Techniques for a 1.8-V-Only NAND Flash Memory. IEEE Journal of Solid state circuits, Vol. 37, NO. 1, Jan 2002. T. Tanzawa, T. Tanaka, K. Takeuchi, and H. Nakamura, Circuit Techniques for a 1.8-V-Only NAND Flash Memory. IEEE Journal of Solid state circuits, Vol. 37, NO. 1, Jan 2002.
19.
Zurück zum Zitat Jedec standard JESD91A-JEP122 Method for Developing Acceleration Models for Electronic Component Failure Mechanisms, www.jedec.org Jedec standard JESD91A-JEP122 Method for Developing Acceleration Models for Electronic Component Failure Mechanisms, www.​jedec.​org
20.
Zurück zum Zitat Jedec standard JESD22a117b Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Stress Test, www.jedec.org Jedec standard JESD22a117b Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Stress Test, www.​jedec.​org
Metadaten
Titel
NAND design for testability and testing
verfasst von
Andrea Silvagni
Copyright-Jahr
2010
Verlag
Springer Netherlands
DOI
https://doi.org/10.1007/978-90-481-9431-5_15

Neuer Inhalt