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Microsystem Technologies
Erschienen in: Microsystem Technologies 4/2020

04.10.2019 | Technical Paper

Negative bias temperature instability (NBTI) effects on p-Si/n-InGaAs hybrid CMOSFETs for digital applications

verfasst von: Suchismita De, Suchismita Tewari, Abhijit Biswas

Erschienen in: Microsystem Technologies | Ausgabe 4/2020

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Abstract

This paper reports, for the first time, the influence of pMOS-negative-bias-temperature-instability (pMOS-NBTI) on the logic performance degradation of a hybrid CMOS inverter, comprising Si pMOS and In0.70Ga0.30As nMOS device, followed by a three-stage-ring-oscillator. The logic performance of an inverter is investigated in terms of high noise margin (NMH), rise time (tr), delay (td), and that for oscillators with reference to frequency of oscillations (fosc). Obtained results show percentage degradation values of 15.38%, 42.90%, 34.09%, and 23.44% for NMH, tr, td, and fosc, respectively, for a stress time of 10 s. It is also found that the oscillation frequency of the ring oscillator degrades ~ 30% for the stress time of 10,000 s compared to without NBTI value.
Vorheriger Artikel Controlled gradual and local thinning of free-standing nanometer thick Si3N4 films using reactive ion etch
Nächster Artikel Capacitive sensor for vehicle obstacle detection, especially for pedestrian detection

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Metadaten
Titel
Negative bias temperature instability (NBTI) effects on p-Si/n-InGaAs hybrid CMOSFETs for digital applications
verfasst von
Suchismita De
Suchismita Tewari
Abhijit Biswas
Publikationsdatum
04.10.2019
Verlag
Springer Berlin Heidelberg
Erschienen in
Microsystem Technologies / Ausgabe 4/2020
Print ISSN: 0946-7076
Elektronische ISSN: 1432-1858
DOI
https://doi.org/10.1007/s00542-019-04646-2

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