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Erschienen in:
Network-on-Chip Technology: A Paradigm Shift Kapitel lesen Erstes Kapitel lesen

2014 | OriginalPaper | Buchkapitel

5. NoC-Based System Integration

verfasst von : Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

Erschienen in: Designing 2D and 3D Network-on-Chip Architectures

Verlag: Springer New York

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Abstract

Integrating the NoC subsystem with the core in an MPSoC is hardly trivial. It requires the design of complex NIs as well as tackle the problem of clock distribution, which requires appropriate synchronizers if the system clock cannot be distributed without skew as is often the case. The synchronizers must be reliable and yet minimize additional latency. Moreover, careful floor-planning is required to achieve good performance. Finally, any multi- and many-core environment must also efficiently solve the problem of cache coherence and therefore the NoC must support and even facilitate cache coherence mechanisms.

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Vorheriges Kapitel Power and Thermal Effects and Management
Nächstes Kapitel NoC Verification and Testing
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Metadaten
Titel
NoC-Based System Integration
verfasst von
Konstantinos Tatas
Kostas Siozios
Dimitrios Soudris
Axel Jantsch
Copyright-Jahr
2014
Verlag
Springer New York
Buch
Designing 2D and 3D Network-on-Chip Architectures

Print ISBN: 978-1-4614-4273-8

Electronic ISBN: 978-1-4614-4274-5

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-1-4614-4274-5_5

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