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Erschienen in:
Network-on-Chip Technology: A Paradigm Shift Kapitel lesen Erstes Kapitel lesen

2014 | OriginalPaper | Buchkapitel

2. NoC Modeling and Topology Exploration

verfasst von : Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

Erschienen in: Designing 2D and 3D Network-on-Chip Architectures

Verlag: Springer New York

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Abstract

This chapter describes two of the most important tasks for designing NoC-based systems dealing with NoC modeling, as well as the topology exploration. For this purpose, state-of-the-art architectural solutions are discussed and open research topics are highlighted. Additionally, this chapter provides a description of alternative traffic models used as input to the NoC domain for evaluating the efficiency of various architectural parameters. The last topics discussed in this chapter are topology synthesis and application mapping onto the derived NoC architecture under various constraints.

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Vorheriges Kapitel Network-on-Chip Technology: A Paradigm Shift
Nächstes Kapitel Communication Architecture
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Metadaten
Titel
NoC Modeling and Topology Exploration
verfasst von
Konstantinos Tatas
Kostas Siozios
Dimitrios Soudris
Axel Jantsch
Copyright-Jahr
2014
Verlag
Springer New York
Buch
Designing 2D and 3D Network-on-Chip Architectures

Print ISBN: 978-1-4614-4273-8

Electronic ISBN: 978-1-4614-4274-5

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-1-4614-4274-5_2

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