For System on-chip (SoC) designs in current Deep Submicron (DSM) era, the performance factors such as propagation delay, power dissipation and crosstalk in
modeled interconnects are the major design concerns. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition in previous state of wire as well as when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. This paper proposes encoding schemes to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses.
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