Anzeige
Erschienen in:
2012 | OriginalPaper | Buchkapitel
Null Convention Logic Circuits Using Balanced Ternary on SOI
verfasst von : Sameh Andrawes, Paul Beckett
Erschienen in: Proceedings of the 2011 2nd International Congress on Computer Applications and Computational Science
Verlag: Springer Berlin Heidelberg
Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.
Wählen Sie Textabschnitte aus um mit Künstlicher Intelligenz passenden Patente zu finden. powered by
Markieren Sie Textabschnitte, um KI-gestützt weitere passende Inhalte zu finden. powered by
We propose and analyze novel Ternary logic circuits targeting an asynchronous Null Convention Logic (NCL) pipeline where the Null value (i.e. Data not valid) is used to make the pipeline self-synchronizing and delay insensitive. A balanced Ternary logic system is used, in which the logic set {High Data, Null, Low Data} maps to voltage levels {+V
DD
, 0V, -V
DD
}. Low power circuits such as Ternary to Binary converter, DATA/NULL Detector and Ternary Register are described based a 45nm SOI process technology that offers multiple simultaneous transistor thresholds.