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This book is based on the 18 presentations during the 21st workshop on Advances in Analog Circuit Design. Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.



Nyquist A/D Converters

Chapter 1. High Performance Piplined A/D Converters in CMOS and BiCMOS Processes

This paper describes the design approach and trade-offs in designing high-speed and high performance pipelined A/D converters in CMOS and BiCMOS processes. Design techniques to improve the linearity, lower the noise and reduce the power consumption will be discussed. The discussion will be in the context of a 16-bit 250 MS/s ADC fabricated on a 0.18 μm BiCMOS process. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, with an input buffer that consumes 150 mW from a 3 V supply. The measured SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency.
Ahmed M. A. Ali

Chapter 2. A 12-bit 800 MS/s Dual-Residue Pipeline ADC

This paper presents the design of a pipeline analog-to-digital converter (ADC) based on the dual-residue principle. By applying this technique, the ADC becomes insensitive to the exact gain of the MDAC residue amplifiers. This allows these amplifiers to be designed with a relatively low open-loop gain and low bandwidth, which is favorable for the power consumption of the ADC. The offsets of the residue amplifiers, however, limit the accuracy of the ADC. Therefore, offset calibration is required for the ADC to achieve a high resolution.
A 12-bit 800 MS/s dual-residue ADC was designed and implemented in a standard 40 nm CMOS technology. The high sampling speed was obtained through four times interleaving. The ADC achieves a peak SNDR of 59 dB. It operates from a dual 1 V/2.5 V power supply and consumes 105 mW.
Jan Mulder, Davide Vecchi, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult

Chapter 3. Time-Interleaved SAR and Slope Converters

This paper investigates time-interleaved SAR and time-interleaved slope converters, targeting low-power, low-resolution, high-speed applications. Fundamentally, these two architectures can be relatively power-efficient as compared to other architectures. At the same time, complex calibration schemes are not required thanks to their inherent accuracy. The architectures are examined and compared, circuit implementations and measurement results are discussed and an outlook to the future will be given.
Pieter Harpe, Ming Ding, Ben Büsze, Cui Zhou, Kathleen Philips, Harmke de Groot

Chapter 4. GS/s AD Conversion for Broadband Multi-stream Reception

In this paper we present a fully integrated solution for broadband multi-stream reception, based on the direct sampling receiver architecture. The key enabler of such a solution is a 64-times interleaved 2.6 GS/s 10 b Successive-Approximation-Register ADC. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. It is used in a fully integrated direct sampling receiver for DOCSIS 3.0 including a digital multi-channel selection filter and a PLL. The ADC achieves an SNDR of 48.5 dB and a THD of less than − 58 dB at Nyquist with an input signal of 1.4Vpp − diff. It consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm2 in 65 nm CMOS.
Erwin Janssen, Athon Zanikopoulos, Kostas Doris, Claudio Nani, Gerard van der Weide

Chapter 5. CMOS Ultra-High-Speed Time-Interleaved ADCs

CMOS technologies have been able to fabricate ultra-high-speed time-interleaved (TI) ADCs that achieve a sampling rate over 10 GS/s. The TI architecture relaxes the speed requirement for each A/D channel. It also introduces inter-channel mismatches that cause conversion errors. These errors can be reduced by calibration. An 8-channel 6-bit 16-GS/s TI ADC is presented to illustrate several circuit design and calibration techniques. Each A/D channel is a 6-bit flash ADC. The low-power comparators in the flash ADC are latches with offset calibration. A delay-locked loop generates the 8-phase sampling clocks for the TI ADC. Timing-skew calibration is used to ensure uniform sampling intervals. Both the offset calibration and the timing-skew calibration run continuously in the background. This TI ADC was fabricated using a 65 nm CMOS technology. At 16 GS/s sampling rate, this chip consumes 435 mW from a 1.5V supply. It achieves a signal-to-distortion-plus-noise ratio (SNDR) of 30.8 dB. The ADC active area is \( 0.93 \times 1.58{\text{ m}}{{\text{m}}^2} \)
Jieh-Tsorng Wu, Chun-Cheng Huang, Chung-Yi Wang

Chapter 6. CMOS ADCs for Optical Communications

This paper provides a systematic view of ADCs embedded in DSP receivers of coherent optical communications systems. The functionality, performance and CMOS implementation trade-offs are discussed with the focus on techniques achieving high sampling rate and bandwidth. High conversion rate is efficiently addressed by massive interleaving of lower speed SAR ADCs, while the bandwidth limitation is dealt with on both architectural and circuit design levels. In conclusion, results of a 40 Gs/s 6b-ADC implemented in 65 nm CMOS are demonstrated.
Yuriy M. Greshishchev

Capacitive Sensor Interfaces

Chapter 7. Motion MEMS and Sensors, Today and Tomorrow

Only 6 years passed since the dawn of the Motion Sensors Era in the Consumer market and now the world of MEMS Motion Sensors is completely different and it’s going to change even more in the future. If 2006 was the year of the Accelerometer adoption by NintendoTM in the WiiTM Controller, 2010 was the year of the Gyroscope adoption by Smartphone manufacturers. And in both cases STMicroelectronics triggered the big volume production of those two micro-machined devices, previously known only by automotive customers and used only for active and passive safety applications. Moreover nowadays combinations of these two inertial products, also known as Six Degree-Of-Freedom Motion Sensors 6XDOF, are starting to appear in the market and most likely they will coexist with standalone accelerometers and gyroscopes, depending on customer needs in terms of compactness and performances. This paper reports the details of an innovative tri-axis silicon MEMS Coriolis’ gyroscope that fulfills the pressing market requirements for low power consumption, small size, slim form factor, high performances and low cost, but it addresses also the recent trends of the Six Degree-Of-Freedom 6XDOF and Nine-Degree-of-Freedom 9XDOF systems, realized by integrating the 6XDOF with a compass.
Benedetto Vigna, E. Lasalandra, T. Ungaretti

Chapter 8. Energy-Efficient Capacitive Sensor Interfaces

Capacitive sensor systems are potentially highly energy efficient. In practice, however, their energy consumption is typically dominated by that of the interface circuit that digitizes the sensor capacitance. Energy-efficient capacitive sensor interfaces are therefore a prerequisite for the successful application of capacitive sensors in energy-constrained applications, such as battery-powered devices and wireless sensor nodes. This chapter derives lower bounds on the energy consumption of capacitive sensor interfaces. A comparison of these bounds with the state-of-the-art suggests that there is significant room for improvement. Several approaches to improving energy efficiency are discussed and illustrated by two design examples.
Michiel A. P. Pertijs, Zhichao Tan

Chapter 9. Interface Circuits for MEMS Microphones

This paper presents an overview of interface circuits for capacitive MEMS microphones. The interface circuits and the building blocks are analyzed in detail, highlighting the most important design issues and trade-offs. Moreover, two design examples are reported, including circuit details and experimental results. The first example is based on a conventional constant-charge approach, while the second introduces the force-feedback concept. Both examples are implemented in a 0.35-μm CMOS technology and achieve a signal-to-noise and distortion ratio larger than 60 dB with a power consumption of about 1 mW from a 3.3-V power supply.
Piero Malcovati, Marco Grassi, Andrea Baschirotto

Chapter 10. Front End Electronics for Solid State Detectors in Today and Future High Energy Physics Experiments

We present circuit design techniques currently employed for the development of analog front end electronics dedicated to the readout of radiation semiconductor sensors used in tracking detectors for High Energy Physics (HEP) experiments, where the channel counts can be very large. It is shown that for very large numbers of channels, power consumption turns out to be a critical issue in the design of the analog front end. In general, Signal-to-Noise-Ratio (SNR) and speed requirements have to be optimized together with the permitted power consumption. A selection of amplifier circuits are discussed in the context of the evolution of the CMOS technologies that impose the adaptation of design techniques to the new properties of deep scaled MOS transistors.
Jan Kaplon, Pierre Jarron



Chapter 11. How Can Chips Live Under Radiation?

Interactions of different types of radiation in silicon are discussed together with effects on devices. Long-term irradiations cause ‘Total-Ionization-Dose’ degradation and ‘Single Event Effects’ occur when dense ionization upsets a small area in a chip. At the CERN Large Hadron Collider LHC we expect a severe radiation environment, yet sophisticated chips are needed. Some remedies against radiation effects are illustrated. One can use changes in technology, in device geometry, in circuit design or in layout. At system level one can recover loss of functions or data. Trends in CMOS technology call for continuous study of behaviour of new devices under radiation. The increased use of chips for critical functions everywhere imposes study of rare effects of radiation, not only in extreme conditions. With large areas of silicon in operation worldwide, low probabilities do result in real incidents.
Erik H. M. Heijne

Chapter 12. Radiation-Tolerant MASH Delta-Sigma Time-to-Digital Converters

Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog signals in time domain. A short survey on state-of-the-art TDCs is given. In order to realize a TDC with picoseconds time resolution as well as multi MGy gamma-dose radiation tolerance, a third-order time-domain ΔΣ TDC structure is proposed. The first prototyping TDC, implemented in 0.13 μm, consumes only 1.7 mW from a 1.2 V supply. It achieves a time resolution of 5.6 ps and an ENOB of 11 bits, when the oversampling ratio (OSR) is 250. The SNDR is mainly limited by the skew error introduced by the comparator delay, which can be mitigated by using a delay-line assisted calibration technique. It improves the ENOB of the TDC to 13 bits and achieves a wide input dynamic range of 100-ns. The TDC also exhibits enhanced radiation tolerance owing to the mismatch-insensitive nature of the ΔΣ structure. Even after a total dose of 3.4 MGy at a high dose rate of 30 kGy/h, the ENOB only drops by 1 bit and, for an OSR of 250, a 10.5 ps time resolution is still achieved.
Ying Cao, Paul Leroux, Wouter De Cock, Michiel Steyaert

Chapter 13. A Designer’s View on Mismatch

Variability consists of systematic and random components. Many systematic effects can be minimized or circumvented by proper lay-out and dedicated design guide lines. Random variations or “mismatch” between equally designed components are often inherent to the device construction. An overview of the mechanisms and mitigation options is presented as viewed by a designer.
Marcel Pelgrom, Hans Tuinhout, Maarten Vertregt

Chapter 14. Analog Circuit Design in Organic Thin-Film Transistor Technologies on Foil: An Overview

In this work an overview is given of the progress which is made in the last few years in the domain of analog organic electronics. Subsequently several building blocks for organic smart sensor systems are brought into focus. The implementations of a two-stage DC-connected opamp, a ΔΣ ADC, a Dickson DC-DC up-converter and a capacitive touch sensor are presented. Special attention is spent to the design techniques applied for embedding the circuits in the given organic electronics technology.
Hagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans

Chapter 15. Impact of Statistical Variability on FinFET Technology: From Device, Statistical Compact Modelling to Statistical Circuit Simulation

New variability resilient device architectures will be required at the 22 nm CMOS technology node and beyond due to the ever-increasing statistical variability in traditional bulk MOSFETs. A TCAD-based Preliminary Design Kit (PDK) development strategy is present here for a 10 nm SOI FinFET technology, with reliable device statistical variability coming from the comprehensive 3D statistical device simulation and accurate statistical compact modelling. Results from the statistical simulation of a 6T SRAM cell demonstrate the advantages of FinFET technology.
A. Asenov, B. Cheng, A. R. Brown, X. Wang
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